Random TestBench don't use Hardcoded values like linear testbenchs. Input stimulus is generated using random values. In Verilog, system function $random provides a mechanism for generating random numbers. The function returns a new 32-bit random number each time it is called. These test cases are not easily readable and are also not reusable. New tests have to be created when the specification or design changes, to accommodate the changes. The main disadvantage of this testing is that we never know what random values are generated and it may waste simulation cycles by generating same values again and again.

EXAMPLE: Linear Random TestBench
module adder(a,b,c); //DUT code start
input [15:0] a,b;
output [16:0] c;
assign c = a + b;
endmodule //DUT code end

module top(); //TestBench code start
reg [15:0] a;
reg [15:0] b;
wire [16:0] c;

adder DUT(a,b,c); //DUT Instantiation

repeat(100) begin
a = $random; //apply random stimulus
b = $random;
#10 $display(" a=%0d,b=%0d,c=%0d",a,b,c);
endmodule //TestBench code end

Asic Design
Bottle Neck In Asic Flow
Functional Verification Need
Linear Testbench
Linear Random Testbench
How To Check The Results
Self Checking Testbenchs
How To Get Scenarios Which We Never Thought
How To Check Whether The Testbench Has Satisfactorily Exercised The Design
Types Of Code Coverage
Statement Coverage
Block Coverage
Conditional Coverage
Branch Coverage
Path Coverage
Toggle Coverage
Fsm Coverage
Make Your Goal 100 Percent Code Coverage Nothing Less
Functional Coverage
Coverage Driven Constraint Random Verification Architecture
Phases Of Verification
Ones Counter Example
Verification Plan

Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!




copyright 2007-2017 :: all rights reserved www.testbench.in::Disclaimer