How does a Verification engineer check whether the results obtained from the simulation match the original specification of the design? For simple testbenchs like the above, output is displayed in waveform window or messages are sent to terminal for visual checking. Visually checking is the oldest and most labor intensive technique. The quality of the verification depends on the determination and dedication of the individual who is doing the checking. It is not practical to verify a complex model merely by examining the waveform or text file. Whenever a change is made to the DUT to add a new feature or to fix a bug, same amount of effort needs to be deployed to check the simulation results.