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INDEX


............INTRODUCTION
..................... Test Bench Overview

............LINEAR TB
..................... Linear Testbench

............FILE IO TB
..................... File I/O Based Testbench

............STATE MACHINE BASED TB

............TASK BASED TB
..................... Task And Function Based Tb

............SELF CHECKING TESTBENCH
..................... Stimulus Generator
..................... Bus Functional Models
..................... Driver
..................... Reciver
..................... Protocol Monitor
..................... Scoreboard
..................... Checker
..................... Coverage
..................... Code Coverage
..................... Functional Coverage

............VERIFICATION FLOW
..................... Planning
..................... Feature Extraction
..................... Verification Environment Architecture Plan

............CLOCK GENERATOR
..................... Timescale And Precision Enlightment

............SIMULATION
..................... Simulation Steps
..................... Macro Preprocessing
..................... Compilation (Analyzer)
..................... Elaboration
..................... Optimization
..................... Initialization
..................... Execution
..................... Simulation Process

............INCREMENTAL COMPILATION

............STORE AND RESTORE

............EVENT CYCLE SIMULATION
..................... Event Based Simulation
..................... Cycle Based Simulation

............TIME SCALE AND PRECISION
..................... Time Scale And Time Precision
..................... $Time Vs $Realtime
..................... System Task Printtimescale
..................... System Task Timeformat

............STIMULUS GENERATION

............SYSTEM FUNCTION RANDOM A MYTH

............RACE CONDITION
..................... What Is Race Condition?
..................... Why Race Condition?
..................... When Race Is Visible?
..................... How To Prevent Race Condition?
..................... Types Of Race Condition
..................... Write-Write Race
..................... Read-Write Race
..................... More Race Example
..................... Event Terminology
..................... The Stratified Event Queue
..................... Determinism
..................... Nondeterminism
..................... Guideline To Avoid Race Condition
..................... Avoid Race Between Testbench And Dut

............CHECKER
..................... Protocol Checker
..................... Data_checker
..................... Modularization

............TASK AND FUNCTION
..................... Functions
..................... Task
..................... Task And Function Queries
..................... Constant Function
..................... Reentrant Tasks And Functions

............PROCESS CONTROL
..................... Nonblocking Task
..................... Fork/Join Recap
..................... Fork/Join None
..................... Fork/Join Any

............DISABLEING THE BLOCK
..................... Disable
..................... Goto
..................... Break
..................... Continue

............WATCHDOG

............COMPILATION N SIMULATION SWITCHS
..................... Compilation And Simulation Directives
..................... Example

............DEBUGGING
..................... Pass Or Fail
..................... Waveform Viewer
..................... Log File
..................... Message Control System
..................... Message Severity Levels
..................... Message Controlling Levels
..................... Passing Comments To Waveform Debugger
..................... $Display N $Strobe
..................... Who Should Do The Rtl Debugging?

............ABOUT CODE COVERAGE
..................... Types Of Coverage
..................... Code Coverage
..................... Statement Coverage /Line Coverage
..................... Block/Segment Coverage
..................... Branch / Decision / Conditional Coverage
..................... Path Coverage
..................... Expression Coverage
..................... Toggle Coverage
..................... Variable Coverage
..................... Triggering / Event Coverage
..................... Parameter Coverage
..................... Functional Coverage
..................... Fsm Coverage
..................... State Coverage
..................... Transition Coverage
..................... Sequence Coverage
..................... Tool Support
..................... Limitation Of Code Coverage

............TESTING STRATIGIES
..................... Bottom-Up
..................... Unit Level
..................... Sub-Asic Level
..................... Asic Level
..................... System Level
..................... Flat

............FILE HANDLING
..................... Fopen And Fclose
..................... Fdisplay
..................... Fmonitor
..................... Fwrite
..................... Mcd
..................... Formating Data To String

............VERILOG SEMAPHORE
..................... Semaphore In Verilog

............FINDING TESTSENARIOUS
..................... Register Tests
..................... System Tests
..................... Interrupt Tests
..................... Interface Tests
..................... Functional Tests
..................... Error Tests
..................... Golden Tests
..................... Performance Tests

............HANDLING TESTCASE FILES

............TERIMINATION

............ERROR INJUCTION
..................... Value Errors
..................... Temporal Errors
..................... Interface Error
..................... Sequence Errors

............REGISTER VERIFICATION
..................... Register Verification
..................... Register Classification
..................... Features

............PARAMETERISED MACROS

............WHITE GRAY BLACK BOX
..................... Black Box Verification
..................... White Box Verification
..................... Gray Box Verification

............REGRESSION

............TIPS
..................... How To Avoid "Module Xxx Already Defined" Error
..................... Colourful Messages
..................... Debugging Macros

Index
Introduction
Linear Tb
File Io Tb
State Machine Based Tb
Task Based Tb
Self Checking Testbench
Verification Flow
Clock Generator
Simulation
Incremental Compilation
Store And Restore
Event Cycle Simulation
Time Scale And Precision
Stimulus Generation
System Function Random A Myth
Race Condition
Checker
Task And Function
Process Control
Disableing The Block
Watchdog
Compilation N Simulation Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Finding Testsenarious
Handling Testcase Files
Terimination
Error Injuction
Register Verification
Parameterised Macros
White Gray Black Box
Regression
Tips

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