Linear TestBench approach to TestBench creation is especially bad for performance. As this is simplest, fastest and easiest way of writing testbenchs, this became novice verification engineer choice. Small models like simple state machine can be verified with this approach. The following code snippet shows linear testbench. Development time increases exponentially as the number of scenarios increases. It is not possible to list all possible input combinations if the number input vectors increases .Just imagine how many inputs are needed to test simple 32 bit adder. Usually Outputs are checked using waveform viewer. As the number of outputs increases, analysis of all the outputs is nightmare. There is no controllability in this method. To test another scenario like read operation, full test bench need to be coded. The simulator must evaluate and schedule a very large number of events. This reduces simulation performance in proportion to the size of the stimulus process.
Linear test bench for a memory model.
initial begin # 10 read_write = 1; address = 100 ; data = 10;
# 10 read_write = 1; address = 101 ; data = 11;
# 10 read_write = 1; address = 102 ; data = 12;
# 10 read_write = 1; address = 103 ; data = 13;
# 10 read_write = 1; address = 104 ; data = 14;