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HANDLING TESTCASE FILES




A test case is a file that describes an input, action, or event and an expected response, to determine if a feature of an application is working correctly. A test case should contain particulars such as test case identifier, test case name, objective, test conditions/setup, input data requirements, steps, and expected results.

Note that the process of developing test cases can help find problems in the requirements or design of an application, since it requires completely thinking through the operation of the application. For this reason, it's useful to prepare test cases early in the development cycle if possible.


The following example contains testbench environment and has 2 test cases.



EXAMPLE: top.v

module top();
// DUT instance, clock generator and TB components

// some tasks

task write()
begin
// some logic
end
endtask

task read()
begin
// some logic
end
endtask


end

EXAMPLE: testcase_1.v

// Do 10 write operations

EXAMPLE: testcase_2.v

// Do 10 read operations




To test first test cases, We have to simulate the contents of top.v file and testcase_1.v file.

1) Take an instance of module TEST in top.v file. Define the module definition in test cases.

During compilation just use the following commands

for testcase_1.v file
comile_command top.v testcase_1.v

for testcase_2.v file
comile_command top.v testcase_2.v





EXAMPLE: top.v

module top();
// DUT instance, clock generator and TB components

// some tasks

task write()
begin
// some logic
end
endtask

task read()
begin
// some logic
end
endtask

// TEST case instance

TEST tst();

end

EXAMPLE: testcase_1.v

// Do 10 write operations

module TEST();

initial
repeat(10)
top.write();

endmodule
EXAMPLE: testcase_2.v

// Do 10 read operations

module TEST();

initial
repeat(10)
top.read();

endmodule



2) use `include test.v file. This needs a small script to copy the testcase file to test file. The compilation command is same. But copy command which copies the testcase to test.v file is different.

During compilation just use the following commands

for testcase_1.v file
cp testcase_1 test.v
comile_command top.v test.v

for testcase_2.v file
cp testcase_2 test.v
comile_command top.v test.v



EXAMPLE: top.v

module top();
// DUT instance, clock generator and TB components

// some tasks

task write()
begin
// some logic
end
endtask

task read()
begin
// some logic
end
endtask

// incule test.v file

`include test.v

end

EXAMPLE: testcase_1.v

// Do 10 write operations

initial
repeat(10)
top.write();


EXAMPLE: testcase_2.v

// Do 10 read operations

initial
repeat(10)
top.read();



2) With the above two approaches, for each test case, we have to do individual compilation. In this method, compile once and use simulation command to test with individual test case.

This needs a small script to convert all the test cases to single intermediate file. compilation command is same. During simulation by giving the test case file name, we can include particular testcase.

During compilation just give following command

cat testcase_1.v > test.v
cat testcase_2.v > test.v
compile_command top.v test.v

During simulation ,
for each test case, use

run_command +testcase_1
run_coomand +testcase_2


EXAMPLE: top.v

module top();
// DUT instance, clock generator and TB components

// some tasks

task write()
begin
// some logic
end
endtask

task read()
begin
// some logic
end
endtask

// incule test.v file

`include test.v

end

EXAMPLE: testcase_1.v

// Do 10 write operations

repeat(10)
top.write();


EXAMPLE: testcase_2.v

// Do 10 read operations

repeat(10)
top.read();



Intermediate file generated contains all the testcase contents with some extra logic as shown.



EXAMPLE: INTERMEDIATE FILE test.v

initial
begin
if($test$plusargs("testcase_1")
begin // testcase_1 contents
// Do 10 write operations
repeat(10)
top.write();
end
if($test$plusargs("testcase_2")
begin // testcase_2 contents
// Do 10 read operations
repeat(10)
top.read();
end
end
Index
Introduction
Linear Tb
File Io Tb
State Machine Based Tb
Task Based Tb
Self Checking Testbench
Verification Flow
Clock Generator
Simulation
Incremental Compilation
Store And Restore
Event Cycle Simulation
Time Scale And Precision
Stimulus Generation
System Function Random A Myth
Race Condition
Checker
Task And Function
Process Control
Disableing The Block
Watchdog
Compilation N Simulation Switchs
Debugging
About Code Coverage
Testing Stratigies
File Handling
Verilog Semaphore
Finding Testsenarious
Handling Testcase Files
Terimination
Error Injuction
Register Verification
Parameterised Macros
White Gray Black Box
Regression
Tips

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