WWW.TESTBENCH.IN - SystemVerilog Constructs

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STRINGS

In Verilog, string literals are packed arrays of a width that is a multiple of 8 bits which hold ASCII values. In Verilog, if a string is larger than the destination string variable, the string is truncated to the left, and the leftmost characters will be lost.  SystemVerilog adds new keyword "string" which is used to declare string data types unlike verilog. String data types can be of arbitrary length and no truncation occurs.

string myName = "TEST BENCH";

String Methods :

SystemVerilog also includes a number of special methods to work with strings. These methods use the built-in method notation. These methods are:
1.      str.len() returns the length of the string, i.e., the number of characters in the string.
2.      str.putc(i, c) replaces the ith character in str with the given integral value.
3.      str.getc(i) returns the ASCII code of the ith character in str.
4.      str.toupper() returns a string with characters in str converted to uppercase.
5.      str.tolower() returns a string with characters in str converted to lowercase.
6.      str.compare(s) compares str and s, and return value. This comparison is case sensitive.
7.      str.icompare(s) compares str and s, and return value  .This comparison is case insensitive.
8.      str.substr(i, j) returns a new string that is a substring formed by index i through j of str.
9.      str.atoi() returns the integer corresponding to the ASCII decimal representation in str.
10.     str.atoreal() returns the real number corresponding to the ASCII decimal representation in str.
11.     str.itoa(i) stores the ASCII decimal representation of i into str (inverse of atoi).
12.     str.hextoa(i) stores the ASCII hexadecimal representation of i into str (inverse of atohex).
13.     str.bintoa(i) stores the ASCII binary representation of i into str (inverse of atobin).
14.     str.realtoa(r) stores the ASCII real representation of r into str (inverse of atoreal)

EXAMPLE : String methods
    module str;
         string A;
         string B;
         initial
         begin
             A = "TEST ";
             B = "Bench";
             $display(" %d ",A.len() );
             $display(" %s ",A.getc(5) );
             $display(" %s ",A.tolower);
             $display(" %s ",B.toupper);
             $display(" %d ",B.compare(A) );
             $display(" %d ",A.compare("test") );
             $display(" %s ",A.substr(2,3) ); A = "111";
             $display(" %d ",A.atoi() );
         end
    endmodule

RESULTS :

           5

test
BENCH
         -18
         -32
ST
         111

String Pattren Match

Use the following method for pattern matching in SystemVerilog. Match method which is in OpenVera or C , is not available in SystemVerilog . For using match method which is in C , use the DPI calls . For native SystemVerilog string match method, hear is the example.

CODE:
   function match(string s1,s2);
       int l1,l2;
       l1 = s1.len();
       l2 = s2.len();
       match = 0 ;
       if( l2 > l1 )
           return 0;
       for(int i = 0;i < l1 - l2 + 1; i ++)
           if( s1.substr(i,i+l2 -1) == s2)
               return 1;
   endfunction

EXAMPLE:
    program main;

    string str1,str2;
    int i;


    initial
    begin
        str1 = "this is first string";
        str2 = "this";
        if(match(str1,str2))
            $display(" str2 : %s : found in :%s:",str2,str1);

        str1 = "this is first string";
        str2 = "first";
        if(match(str1,str2))
            $display(" str2 : %s : found in :%s:",str2,str1);

        str1 = "this is first string";
        str2 = "string";
        if(match(str1,str2))
            $display(" str2 : %s : found in :%s:",str2,str1);

        str1 = "this is first string";
        str2 = "this is ";
        if(match(str1,str2))
            $display(" str2 : %s : found in :%s:",str2,str1);

        str1 = "this is first string";
        str2 = "first string";
        if(match(str1,str2))
            $display(" str2 : %s : found in :%s:",str2,str1);

        str1 = "this is first string";
        str2 = "first string ";// one space at end
        if(match(str1,str2))
            $display(" str2 : %s : found in :%s:",str2,str1);

    end

    endprogram

RESULTS:

str2 : this : found in :this is first string:
str2 : first : found in :this is first string:
str2 : string : found in :this is first string:
str2 : this is : found in :this is first string:
str2 : first string : found in :this is first string:

String Operators

SystemVerilog provides a set of operators that can be used to manipulate combinations of string variables and string literals. The basic operators defined on the string data type are

Equality

Syntax : Str1 == Str2

Checks whether the two strings are equal. Result is 1 if they are equal and 0 if they are not. Both strings can be of type string. Or one of them can be a string literal. If both operands are string literals, the operator is the same Verilog equality operator as for integer types.

EXAMPLE
   program main;
      initial
      begin
          string str1,str2,str3;
          str1 = "TEST BENCH";
          str2 = "TEST BENCH";
          str3 = "test bench";
          if(str1 == str2)
              $display(" Str1 and str2 are equal");
          else
              $display(" Str1 and str2 are not equal");
          if(str1 == str3)
              $display(" Str1 and str3 are equal");
          else
              $display(" Str1 and str3 are not equal");

      end
   endprogram

RESULT

Str1 and str2 are equal
Str1 and str3 are not equal

Inequality.

Syntax: Str1 != Str2

Logical negation of Equality operator.  Result is 0 if they are equal and 1 if they are not. Both strings can be of type string. Or one of them can be a string literal. If both operands are string literals, the operator is the same Verilog equality operator as for integer types.

EXAMPLE
   program main;
      initial
      begin
         string str1,str2,str3;
         str1 = "TEST BENCH";
         str2 = "TEST BENCH";
         str3 = "test bench";
         if(str1 != str2)
             $display(" Str1 and str2 are not equal");
         else
             $display(" Str1 and str2 are equal");
         if(str1 != str3)
             $display(" Str1 and str3 are not equal");
         else
             $display(" Str1 and str3 are equal");

      end
   endprogram
RESULT

Str1 and str2 are equal
Str1 and str3 are not equal

Comparison.

Syntax:
Str1 < Str2
Str1 <= Str2
Str1 > Str2
Str1 >= Str2

Relational operators return 1 if the corresponding condition is true using the lexicographical ordering of the two strings Str1 and Str2. The comparison uses the compare string method. Both operands can be of type string, or one of them can be a string literal.

EXAMPLE
   program main;
      initial
      begin
          string Str1,Str2,Str3;
          Str1 = "c";
          Str2 = "d";
          Str3 = "e";

          if(Str1 < Str2)
              $display(" Str1 < Str2 ");
          if(Str1 <= Str2)
              $display(" Str1 <= Str2 ");
          if(Str3 > Str2)
              $display(" Str3 > Str2");
          if(Str3 >= Str2)
              $display(" Str3 >= Str2");
      end
   endprogram

RESULT

Str1 < Str2
Str1 <= Str2
Str3 > Str2
Str3 >= Str2

Concatenation.
Syntax: {Str1,Str2,...,Strn}

Each operand can be of type string or a string literal (it shall be implicitly converted to type string). If at least one operand is of type string, then the expression evaluates to the concatenated string and is of type string. If all the operands are string literals, then the expression behaves like a Verilog concatenation of integral types; if the result is then used in an expression involving string types, it is implicitly converted to the string type.

EXAMPLE
   program main;
       initial
       begin
           string Str1,Str2,Str3,Str4,Str5;
           Str1 = "WWW.";
           Str2 = "TEST";
           Str3 = "";
           Str4 = "BENCH";
           Str5 = ".IN";
           $display(" %s ",{Str1,Str2,Str3,Str4,Str5});
       end
   endprogram

RESULT

WWW.TESTBENCH.IN

Replication.

Syntax : {multiplier{Str}}

Str can be of type string or a string literal. Multiplier must be of integral type and can be nonconstant. If multiplier is nonconstant or Str is of type string, the result is a string containing N concatenated copies of Str, where N is specified by the multiplier. If Str is a literal and the multiplier is constant, the expression behaves like numeric replication in Verilog (if the result is used in another expression involving string types, it is implicitly converted to the string type).

EXAMPLE
    program main;
        initial
        begin
            string Str1,Str2;
            Str1 = "W";
            Str2 = ".TESTBENCH.IN";
            $display(" %s ",{{3{Str1}},Str2});
        end
    endprogram

RESULT

WWW.TESTBENCH.IN

Indexing.
Syntax: Str[index]

Returns a byte, the ASCII code at the given index. Indexes range from 0 to N-1, where N is the number of characters in the string. If given an index out of range, returns 0. Semantically equivalent to Str.getc(index)

EXAMPLE
    program main;
       initial
       begin
          string Str1;
          Str1 = "WWW.TESTBENCH.IN";
          for(int i =0 ;i < 16 ; i++)
             $write("%s ",Str1[i]);
       end
    endprogram

RESULT

W W W . T E S T B E N C H . I N

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