The SystemVerilog operators are a combination of Verilog and C operators. In both languages, the type and size of the operands is fixed, and hence the operator is of a fixed type and size. The fixed type and size of operators is preserved in SystemVerilog. This allows efficient code generation.
Verilog does not have assignment operators or increment and decrement operators. SystemVerilog includes the C assignment operators, such as +=, and the C increment and decrement operators, ++ and --.
Verilog-2001 added signed nets and reg variables, and signed based literals. There is a difference in the rules for combining signed and unsigned integers between Verilog and C. SystemVerilog uses the Verilog rules.
Operators In Systemverilog
Following are the operators in systemverilog
Assignment Operators
In addition to the simple assignment operator, =, SystemVerilog includes the C assignment operators and special bitwise assignment operators:
An assignment operator is semantically equivalent to a blocking assignment, with the exception that any left-hand side index expression is only evaluated once.
For example:
a[i]+=2; // same as a[i] = a[i] +2;
Following are the new SystemVerilog assignment operators and its equivalent in verilog
Assignments In Expression
In SystemVerilog, an expression can include a blocking assignment. such an assignment must be enclosed in parentheses to avoid common mistakes such as using a=b for a==b, or a|=b for a!=b.
if ((a=b)) b = (a+=1); // assign b to a
a = (b = (c = 5));// assign 5 to c
if(a=b) // error in systemverilog
(a=b) statement assigns b value to a and then returns a value.
if((a=b)) is equivalent to
a=b;
if(a)
EXAMPLE module assignment();
int a,b,c;
initialbegin a = 1; b =2;c =3;
if((a=b))
$display(" a value is %d ",a);
a = (b = (c = 5));
$display(" a is %d b is %d c is %d ",a,b,c);
end
endmodule RESULT
a value is 2 a is 5 b is 5 c is 5
Concatenation :
{} concatenation right of assignment.
´{} concatenation left of assignment.
EXAMPLE :Concatenation program main ;
bit [4:0] a;
reg b,c,d;
initialbegin b = 0;
c = 1;
d = 1;
a = {b,c,0,0,d};
{b,c,d} = 3'b111;
$display(" a %b b %b c %b d %b ",a,b,c,d);
end endprogram
RESULTS
a 00001 b 1 c 1 d 1
Arithmetic :
EXAMPLE :Arithmetic program main;
integer a,b;
initial begin b = 10;
a = 22;
$display(" -(nagetion) is %0d ",-(a) );
$display(" a + b is %0d ",a+b);
$display(" a - b is %0d ",a-b);
$display(" a * b is %0d ",a*b);
$display(" a / b is %0d ",a/b);
$display(" a modulus b is %0d ",a%b);
end endprogram
RESULTS
-(nagetion) is -22 a + b is 32 a - b is 12 a * b is 220 a / b is 2 a modules b is 2
Following tabel shows the opwer operator rules for calculating the result.
EXAMPLE :Relational program main ;
integer a,b;
initial begin b = 10;
a = 22;
$display(" a < b is %0d \n",a < b);
$display(" a > b is %0d \n",a >b);
$display(" a <= b is %0d \n",a <= b);
$display(" a >= b is %0d \n",a >= b);
end endprogram RESULTS
a < b is 0 a > b is 1 a <= b is 0 a >= b is 1
Equality :
The different types of equality (and inequality) operators in SystemVerilog behave differently when their operands contain unknown values (X or Z). The == and != operators may result in X if any of their operands contains an X or Z. The === and !== check the 4-state explicitly, therefore, X and Z values shall either match or mismatch, never resulting in X. The ==? and !=? operators may result in X if the left operand contains an X or Z that is not being compared with a wildcard in the right operand.
EXAMPLE : logical Equality program main;
reg[3:0] a;
reg[7:0] x, y, z;
initialbegin a = 4'b0101;
x = 8'b1000_0101;
y = 8'b0000_0101;
z = 8'b0xx0_0101;
if (x == a)
$display("x equals a is TRUE.\n");
if (y == a)
$display("y equals a is TRUE.\n");
if (z == a)
$display("z equals a is TRUE.\n");
end endprogram RESULTS:
-------------------------- == 0 1 x z -------------------------- 0 1 0 x x 1 0 1 x x x x x x x z x x x x -------------------------- -------------------------- === 0 1 x z -------------------------- 0 1 0 0 0 1 0 1 0 0 x 0 0 1 0 z 0 0 0 1 -------------------------- -------------------------- =?= 0 1 x z -------------------------- 0 1 0 1 1 1 0 1 1 1 x 1 1 1 1 z 1 1 1 1 -------------------------- -------------------------- != 0 1 x z -------------------------- 0 0 1 x x 1 1 0 x x x x x x x z x x x x -------------------------- -------------------------- !== 0 1 x z -------------------------- 0 0 1 1 1 1 1 0 1 1 x 1 1 0 1 z 1 1 1 0 -------------------------- -------------------------- !?= 0 1 x z -------------------------- 0 0 1 0 0 1 1 0 0 0 x 0 0 0 0 z 0 0 0 0 --------------------------