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| //////////////////////////////////////////////// ////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s//// ////s www.testbench.in s//// ////s s//// ////s SystemVerilog Tutorial s//// ////s s//// ////s gopi@testbench.in s//// ////s~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~s//// //////////////////////////////////////////////// interface intf_cnt(input clk); wire clk; wire reset; wire data; wire [0:3] count; endinterface |