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PHASE 3 RESET
In this phase we will reset and configure the DUT.
The Environment class has reset_dut() method which contains the logic to reset the DUT and cfg_dut() method which contains the logic to configure the DUT port address.
NOTE: Clocking block signals can be driven only using a non-blocking assignment.
In reset_dut() method.
1) Set all the DUT input signals to a known state. And reset the DUT.
virtual task reset_dut();
super.reset_dut();
`vmm_note(this.log,"Start of reset_dut() method ");
mem_intf.cb.mem_data <= 0;
mem_intf.cb.mem_add <= 0;
mem_intf.cb.mem_en <= 0;
mem_intf.cb.mem_rd_wr <= 0;
input_intf.cb.data_in <= 0;
input_intf.cb.data_status <= 0;
output_intf[0].cb.read <= 0;
output_intf[1].cb.read <= 0;
output_intf[2].cb.read <= 0;
output_intf[3].cb.read <= 0;
// Reset the DUT
input_intf.reset <= 1;
repeat (4) @ input_intf.clock;
input_intf.reset <= 0;
`vmm_note(this.log,"End of reset_dut() method ");
endtask
2) Updated the cfg_dut method.
virtual task cfg_dut();
super.cfg_dut();
`vmm_note(this.log,"Start of cfg_dut() method ");
mem_intf.cb.mem_en <= 1;
@(posedge mem_intf.clock);
mem_intf.cb.mem_rd_wr <= 1;
@(posedge mem_intf.clock);
mem_intf.cb.mem_add <= 8'h0;
mem_intf.cb.mem_data <= `P0;
`vmm_note(this.log ,$psprintf(" Port 0 Address %h ",`P0));
@(posedge mem_intf.clock);
mem_intf.cb.mem_add <= 8'h1;
mem_intf.cb.mem_data <= `P1;
`vmm_note(this.log ,$psprintf(" Port 1 Address %h ",`P1));
@(posedge mem_intf.clock);
mem_intf.cb.mem_add <= 8'h2;
mem_intf.cb.mem_data <= `P2;
`vmm_note(this.log ,$psprintf(" Port 2 Address %h ",`P2));
@(posedge mem_intf.clock);
mem_intf.cb.mem_add <= 8'h3;
mem_intf.cb.mem_data <= `P3;
`vmm_note(this.log ,$psprintf(" Port 3 Address %h ",`P3));
@(posedge mem_intf.clock);
mem_intf.cb.mem_en <=0;
mem_intf.cb.mem_rd_wr <= 0;
mem_intf.cb.mem_add <= 0;
mem_intf.cb.mem_data <= 0;
`vmm_note(this.log,"End of cfg_dut() method ");
endtask
(3) In wait_for_end method, wait for some clock cycles.
repeat(10000) @(input_intf.clock);
Download the Phase 3 source code:
vmm_switch_3.tar
Browse the code in vmm_switch_3.tar
Run the simulation:
vcs -sverilog -f filelist -R -ntb_opts rvm
Log File report
******************* Start of testcase ****************
Normal[NOTE] on Environment() at 0:
Created env object
Normal[NOTE] on Environment() at 0:
Start of gen_cfg() method
Normal[NOTE] on Environment() at 0:
End of gen_cfg() method
Normal[NOTE] on Environment() at 0:
Start of build() method
Normal[NOTE] on Environment() at 0:
End of build() method
Normal[NOTE] on Environment() at 0:
Start of reset_dut() method
Normal[NOTE] on Environment() at 60:
End of reset_dut() method
Normal[NOTE] on Environment() at 60:
Start of cfg_dut() method
Normal[NOTE] on Environment() at 90:
Port 0 Address 00
Normal[NOTE] on Environment() at 110:
Port 1 Address 11
Normal[NOTE] on Environment() at 130:
Port 2 Address 22
Normal[NOTE] on Environment() at 150:
Port 3 Address 33
Normal[NOTE] on Environment() at 170:
End of cfg_dut() method
Normal[NOTE] on Environment() at 170:
Start of start() method
Normal[NOTE] on Environment() at 170:
End of start() method
Normal[NOTE] on Environment() at 170:
Start of wait_for_end() method
Normal[NOTE] on Environment() at 100170:
End of wait_for_end() method
Normal[NOTE] on Environment() at 100170:
Start of stop() method
Normal[NOTE] on Environment() at 100170:
End of stop() method
Normal[NOTE] on Environment() at 100170:
Start of cleanup() method
Normal[NOTE] on Environment() at 100170:
End of cleanup() method
Normal[NOTE] on Environment() at 100170:
Start of report() method
---------------------------------------------------------------------
Simulation PASSED on /./ (/./) at 100170 (0 warnings, 0 demoted errors & 0 demoted warnings)
---------------------------------------------------------------------
Normal[NOTE] on Environment() at 100170:
End of report() method
******************** End of testcase *****************
In this phase we will reset and configure the DUT.
The Environment class has reset_dut() method which contains the logic to reset the DUT and cfg_dut() method which contains the logic to configure the DUT port address.
NOTE: Clocking block signals can be driven only using a non-blocking assignment.
In reset_dut() method.
1) Set all the DUT input signals to a known state. And reset the DUT.
virtual task reset_dut();
super.reset_dut();
`vmm_note(this.log,"Start of reset_dut() method ");
mem_intf.cb.mem_data <= 0;
mem_intf.cb.mem_add <= 0;
mem_intf.cb.mem_en <= 0;
mem_intf.cb.mem_rd_wr <= 0;
input_intf.cb.data_in <= 0;
input_intf.cb.data_status <= 0;
output_intf[0].cb.read <= 0;
output_intf[1].cb.read <= 0;
output_intf[2].cb.read <= 0;
output_intf[3].cb.read <= 0;
// Reset the DUT
input_intf.reset <= 1;
repeat (4) @ input_intf.clock;
input_intf.reset <= 0;
`vmm_note(this.log,"End of reset_dut() method ");
endtask
2) Updated the cfg_dut method.
virtual task cfg_dut();
super.cfg_dut();
`vmm_note(this.log,"Start of cfg_dut() method ");
mem_intf.cb.mem_en <= 1;
@(posedge mem_intf.clock);
mem_intf.cb.mem_rd_wr <= 1;
@(posedge mem_intf.clock);
mem_intf.cb.mem_add <= 8'h0;
mem_intf.cb.mem_data <= `P0;
`vmm_note(this.log ,$psprintf(" Port 0 Address %h ",`P0));
@(posedge mem_intf.clock);
mem_intf.cb.mem_add <= 8'h1;
mem_intf.cb.mem_data <= `P1;
`vmm_note(this.log ,$psprintf(" Port 1 Address %h ",`P1));
@(posedge mem_intf.clock);
mem_intf.cb.mem_add <= 8'h2;
mem_intf.cb.mem_data <= `P2;
`vmm_note(this.log ,$psprintf(" Port 2 Address %h ",`P2));
@(posedge mem_intf.clock);
mem_intf.cb.mem_add <= 8'h3;
mem_intf.cb.mem_data <= `P3;
`vmm_note(this.log ,$psprintf(" Port 3 Address %h ",`P3));
@(posedge mem_intf.clock);
mem_intf.cb.mem_en <=0;
mem_intf.cb.mem_rd_wr <= 0;
mem_intf.cb.mem_add <= 0;
mem_intf.cb.mem_data <= 0;
`vmm_note(this.log,"End of cfg_dut() method ");
endtask
(3) In wait_for_end method, wait for some clock cycles.
repeat(10000) @(input_intf.clock);
Download the Phase 3 source code:
vmm_switch_3.tar
Browse the code in vmm_switch_3.tar
Run the simulation:
vcs -sverilog -f filelist -R -ntb_opts rvm
Log File report
******************* Start of testcase ****************
Normal[NOTE] on Environment() at 0:
Created env object
Normal[NOTE] on Environment() at 0:
Start of gen_cfg() method
Normal[NOTE] on Environment() at 0:
End of gen_cfg() method
Normal[NOTE] on Environment() at 0:
Start of build() method
Normal[NOTE] on Environment() at 0:
End of build() method
Normal[NOTE] on Environment() at 0:
Start of reset_dut() method
Normal[NOTE] on Environment() at 60:
End of reset_dut() method
Normal[NOTE] on Environment() at 60:
Start of cfg_dut() method
Normal[NOTE] on Environment() at 90:
Port 0 Address 00
Normal[NOTE] on Environment() at 110:
Port 1 Address 11
Normal[NOTE] on Environment() at 130:
Port 2 Address 22
Normal[NOTE] on Environment() at 150:
Port 3 Address 33
Normal[NOTE] on Environment() at 170:
End of cfg_dut() method
Normal[NOTE] on Environment() at 170:
Start of start() method
Normal[NOTE] on Environment() at 170:
End of start() method
Normal[NOTE] on Environment() at 170:
Start of wait_for_end() method
Normal[NOTE] on Environment() at 100170:
End of wait_for_end() method
Normal[NOTE] on Environment() at 100170:
Start of stop() method
Normal[NOTE] on Environment() at 100170:
End of stop() method
Normal[NOTE] on Environment() at 100170:
Start of cleanup() method
Normal[NOTE] on Environment() at 100170:
End of cleanup() method
Normal[NOTE] on Environment() at 100170:
Start of report() method
---------------------------------------------------------------------
Simulation PASSED on /./ (/./) at 100170 (0 warnings, 0 demoted errors & 0 demoted warnings)
---------------------------------------------------------------------
Normal[NOTE] on Environment() at 100170:
End of report() method
******************** End of testcase *****************
Index
Introduction
Specification
Verification Plan
Phase 1 Top
Phase 2 Environment
Phase 3 Reset
Phase 4 Packet
Phase 5 Generator
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
Phase 9 Coverage
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Introduction
Specification
Verification Plan
Phase 1 Top
Phase 2 Environment
Phase 3 Reset
Phase 4 Packet
Phase 5 Generator
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard
Phase 9 Coverage
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!