ahe UVM (Universal Verification Methodology) Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog.

UVM library contains:
Component classes for building testbench components like generator/driver/monitor etc.
Reporting classes for logging,
Factory for object substitution.
Synchronization classes for managing concurrent process.
Policy classes for printing, comparing, recording, packing, and unpacking of uvm_object based classes.
TLM Classes for transaction level interface.
Sequencer and Sequence classes for generating realistic stimulus.
And Macros which can be used for shorthand notation of complex implementation.

In this tutorial, we will learn some of the UVM concepts with examples.

Installing Uvm Library

1)Go to http://www.accellera.org/activities/vip/
2)Download the uvm*.tar.gz file.
3)Untar the file.
4)Go to the extracted directory : cd uvm*\uvm\src
5)Set the UVM_HOME path : setenv UVM_HOME `pwd`
(This is required to run the examples which are downloaded from this site)
6)Go to examples : cd ../examples/hello_world/uvm/
7)Compile the example using :
your_tool_compilation_command -f compile_<toolname>.f
(example for questasim use : qverilog -f compile_questa.f)
8)Run the example.

Uvm Testbench
Uvm Reporting
Uvm Transaction
Uvm Configuration
Uvm Factory
Uvm Sequence 1
Uvm Sequence 2
Uvm Sequence 3
Uvm Sequence 4
Uvm Sequence 5
Uvm Sequence 6
Uvm Tlm 1
Uvm Tlm 2
Uvm Callback

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