1) We will write SystemVerilog Interfaces for input port, output port and memory port.
2) We will write Top module where testcase and DUT instances are done.
3) DUT and interfaces are connected in top module.
4) We will implement Clock generator in top module.
In the interface.sv file, declare the 3 interfaces in the following way.
All the interfaces has clock as input.
All the signals in interface are wire type.
All the signals are synchronized to clock except reset in clocking block.
This approach will avoid race conditions between the design and the verification environment.
Define the set-up and hold time using parameters.
Signal directional w.r.t TestBench is specified with modport.
(S)Interface Source Code
// Interface declaration for the memory///
// Interface for the input side of switch.//
// Reset signal is also passed hear. //
interface input_interface(inputbit clock);
The modules that are included in the source text but are not instantiated are called top modules. This module is the highest scope of modules. Generally this module is named as "top" and referenced as "top module". Module name can be anything.
This top-level module will contain the design portion of the simulation.
Do the following in the top module:
1) The first step is to import the uvm packages
2)Generate the clock signal.
initial begin #20;
forever #10 Clock = ~Clock;
2)Do the instances of memory interface.
3)Do the instances of input interface.
4)There are 4 output ports. So do 4 instances of output_interface.
5) Connect all the interfaces and DUT. The design which we have taken is in verilog. So Verilog DUT instance is connected signal by signal.