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PHASE 1 TOP



In phase 1,

1) We will write SystemVerilog Interfaces for input port, output port and memory port.
2) We will write Top module where testcase and DUT instances are done.
3) DUT and interfaces are connected in top module.
4) We will implement Clock generator in top module.




Interface



In the interface.sv file, declare the 3 interfaces in the following way.
All the interfaces has clock as input.
All the signals in interface are wire type.
All the signals are synchronized to clock except reset in clocking block.

This approach will avoid race conditions between the design and the verification environment.
Define the set-up and hold time using parameters.
Signal directional w.r.t TestBench is specified with modport.



(S)Interface Source Code


`ifndef GUARD_INTERFACE
`define GUARD_INTERFACE


//////////////////////////////////////////
// Interface declaration for the memory///
//////////////////////////////////////////

interface mem_interface(input bit clock);

parameter setup_time = 5ns;
parameter hold_time = 3ns;

wire [7:0] mem_data;
wire [1:0] mem_add;
wire mem_en;
wire mem_rd_wr;

clocking cb@(posedge clock);
default input #setup_time output #hold_time;
output mem_data;
output mem_add;
output mem_en;
output mem_rd_wr;
endclocking:cb

modport MEM(clocking cb,input clock);

endinterface :mem_interface

////////////////////////////////////////////
// Interface for the input side of switch.//
// Reset signal is also passed hear. //
////////////////////////////////////////////
interface input_interface(input bit clock);

parameter setup_time = 5ns;
parameter hold_time = 3ns;

wire data_status;
wire [7:0] data_in;
reg reset;

clocking cb@(posedge clock);
default input #setup_time output #hold_time;
output data_status;
output data_in;
endclocking:cb

modport IP(clocking cb,output reset,input clock);

endinterface:input_interface

/////////////////////////////////////////////////
// Interface for the output side of the switch.//
// output_interface is for only one output port//
/////////////////////////////////////////////////

interface output_interface(input bit clock);

parameter setup_time = 5ns;
parameter hold_time = 3ns;

wire [7:0] data_out;
wire ready;
wire read;

clocking cb@(posedge clock);
default input #setup_time output #hold_time;
input data_out;
input ready;
output read;
endclocking:cb

modport OP(clocking cb,input clock);

endinterface:output_interface

//////////////////////////////////////////////////

`endif

Top Module




The modules that are included in the source text but are not instantiated are called top modules. This module is the highest scope of modules. Generally this module is named as "top" and referenced as "top module". Module name can be anything.
This top-level module will contain the design portion of the simulation.

Do the following in the top module:

1) The first step is to import the uvm packages


`include "uvm.svh"
import uvm_pkg::*;


2)Generate the clock signal.


bit Clock;

initial
begin
#20;
forever #10 Clock = ~Clock;
end


2)Do the instances of memory interface.


mem_interface mem_intf(Clock);


3)Do the instances of input interface.


input_interface input_intf(Clock);


4)There are 4 output ports. So do 4 instances of output_interface.


output_interface output_intf[4](Clock);


5) Connect all the interfaces and DUT. The design which we have taken is in verilog. So Verilog DUT instance is connected signal by signal.



switch DUT (.clk(Clock),
.reset(input_intf.reset),
.data_status(input_intf.data_status),
.data(input_intf.data_in),
.port0(output_intf[0].data_out),
.port1(output_intf[1].data_out),
.port2(output_intf[2].data_out),
.port3(output_intf[3].data_out),
.ready_0(output_intf[0].ready),
.ready_1(output_intf[1].ready),
.ready_2(output_intf[2].ready),
.ready_3(output_intf[3].ready),
.read_0(output_intf[0].read),
.read_1(output_intf[1].read),
.read_2(output_intf[2].read),
.read_3(output_intf[3].read),
.mem_en(mem_intf.mem_en),
.mem_rd_wr(mem_intf.mem_rd_wr),
.mem_add(mem_intf.mem_add),
.mem_data(mem_intf.mem_data));

(S) Top module Scource Code

`ifndef GUARD_TOP
`define GUARD_TOP
/////////////////////////////////////////////////////
// Importing UVM Packages //
/////////////////////////////////////////////////////

`include "uvm.svh"
import uvm_pkg::*;

module top();

/////////////////////////////////////////////////////
// Clock Declaration and Generation //
/////////////////////////////////////////////////////
bit Clock;

initial
begin
#20;
forever #10 Clock = ~Clock;
end
/////////////////////////////////////////////////////
// Memory interface instance //
/////////////////////////////////////////////////////

mem_interface mem_intf(Clock);

/////////////////////////////////////////////////////
// Input interface instance //
/////////////////////////////////////////////////////

input_interface input_intf(Clock);

/////////////////////////////////////////////////////
// output interface instance //
/////////////////////////////////////////////////////

output_interface output_intf[4](Clock);

/////////////////////////////////////////////////////
// DUT instance and signal connection //
/////////////////////////////////////////////////////

switch DUT (.clk(Clock),
.reset(input_intf.reset),
.data_status(input_intf.data_status),
.data(input_intf.data_in),
.port0(output_intf[0].data_out),
.port1(output_intf[1].data_out),
.port2(output_intf[2].data_out),
.port3(output_intf[3].data_out),
.ready_0(output_intf[0].ready),
.ready_1(output_intf[1].ready),
.ready_2(output_intf[2].ready),
.ready_3(output_intf[3].ready),
.read_0(output_intf[0].read),
.read_1(output_intf[1].read),
.read_2(output_intf[2].read),
.read_3(output_intf[3].read),
.mem_en(mem_intf.mem_en),
.mem_rd_wr(mem_intf.mem_rd_wr),
.mem_add(mem_intf.mem_add),
.mem_data(mem_intf.mem_data));


endmodule : top


`endif

(S)Download the files:


uvm_switch_1.tar
Browse the code in uvm_switch_1.tar


(S)Command to compile


VCS Users : make vcs
Questa Users: make questa


Index
Introduction
Specification
Verification Plan
Phase 1 Top
Phase 2 Configuration
Phase 3 Environment N Testcase
Phase 4 Packet
Phase 5 Sequencer N Sequence
Phase 6 Driver
Phase 7 Receiver
Phase 8 Scoreboard

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