Tutorials
PHASE 3 RESET
In this phase we will reset and configure the DUT.
The Environment class has reset() method which contains the logic to reset the DUT and cfg_dut() method which contains the logic to configure the DUT port address.
NOTE : Clocking block signals can be driven only using a non
- blocking assignment
.
Define the reset() method.
1) Set all the DUT input signals to a known state.
mem_intf
. cb
. mem_data
<= 0 ;
mem_intf
. cb
. mem_add
<= 0 ;
mem_intf
. cb
. mem_en
<= 0 ;
mem_intf
. cb
. mem_rd_wr
<= 0 ;
input_intf
. cb
. data_in
<= 0 ;
input_intf
. cb
. data_status
<= 0 ;
output_intf
[ 0 ]. cb
. read
<= 0 ;
output_intf
[ 1 ]. cb
. read
<= 0 ;
output_intf
[ 2 ]. cb
. read
<= 0 ;
output_intf
[ 3 ]. cb
. read
<= 0 ;
2) Reset the DUT.
// Reset the DUT
input_intf
. reset
<= 1 ;
repeat ( 4 ) @ input_intf
. clock
;
input_intf
. reset
<= 0 ;
3) Updated the cfg_dut method.
task cfg_dut
();
$display ( " %0d : Environment : start of cfg_dut() method" , $time );
mem_intf
. cb
. mem_en
<= 1 ;
@( posedge mem_intf
. clock
);
mem_intf
. cb
. mem_rd_wr
<= 1 ;
@( posedge mem_intf
. clock
);
mem_intf
. cb
. mem_add
<= 8'h0 ;
mem_intf
. cb
. mem_data
<= `P0 ;
$display ( " %0d : Environment : Port 0 Address %h " , $time , `P0 );
@( posedge mem_intf
. clock
);
mem_intf
. cb
. mem_add
<= 8'h1 ;
mem_intf
. cb
. mem_data
<= `P1 ;
$display ( " %0d : Environment : Port 1 Address %h " , $time , `P1 );
@( posedge mem_intf
. clock
);
mem_intf
. cb
. mem_add
<= 8'h2 ;
mem_intf
. cb
. mem_data
<= `P2 ;
$display ( " %0d : Environment : Port 2 Address %h " , $time , `P2 );
@( posedge mem_intf
. clock
);
mem_intf
. cb
. mem_add
<= 8'h3 ;
mem_intf
. cb
. mem_data
<= `P3 ;
$display ( " %0d : Environment : Port 3 Address %h " , $time , `P3 );
@( posedge mem_intf
. clock
);
mem_intf
. cb
. mem_en
<= 0 ;
mem_intf
. cb
. mem_rd_wr
<= 0 ;
mem_intf
. cb
. mem_add
<= 0 ;
mem_intf
. cb
. mem_data
<= 0 ;
$display ( " %0d : Environment : end of cfg_dut() method" , $time );
endtask : cfg_dut
(4) In wait_for_end method, wait for some clock cycles.
task wait_for_end
();
$display ( " %0d : Environment : start of wait_for_end() method" , $time );
repeat ( 10000 ) @( input_intf
. clock
);
$display ( " %0d : Environment : end of wait_for_end() method" , $time );
endtask : wait_for_end
(S)Download the Phase 3 source code:
switch_3.tar
Browse the code in switch_3.tar
(S)Run the simulation:
vcs
- sverilog
- f filelist
- R
- ntb_opts dtm
(S)Log File report
******************* Start of testcase ****************
0 : Environment : created env object
0 : Environment : start of run() method
0 : Environment : start of build() method
0 : Environment : end of build() method
0 : Environment : start of reset() method
40 : Environment : end of reset() method
40 : Environment : start of cfg_dut() method
70 : Environment : Port 0 Address 00
90 : Environment : Port 1 Address 11
110 : Environment : Port 2 Address 22
130 : Environment : Port 3 Address 33
150 : Environment : end of cfg_dut() method
150 : Environment : start of start() method
150 : Environment : end of start() method
150 : Environment : start of wait_for_end() method
100150 : Environment : end of wait_for_end() method
100150 : Environment : end of run() method
******************** End of testcase *****************