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TOP
Top level module containts the design and testbench instance. Top module also contains clock generator. There is no need to instantiate the top module.
Testbench and dut instances are connected using wires.
CODE: top.v
module top();
//Declare clock signal
reg clock;
//Signals for Assertion and to view the class proprties in Waveform viewer
wire data_status;
wire [7:0] data_in;
wire [7:0] data_out[0:3];
wire [3:0] ready;
wire [3:0] read;
wire [7:0] mem_data;
wire [1:0] mem_add;
wire reset;
wire mem_en;
wire mem_rd_wr;
wire SystemClock ;
assign SystemClock = clock;
main tb ( .SystemClock (SystemClock),
.\intf.clk (clock),
.\intf.data_status (data_status),
.\intf.data_in (data_in),
.\intf.data_out_0 (data_out[0]),
.\intf.data_out_1 (data_out[1]),
.\intf.data_out_2 (data_out[2]),
.\intf.data_out_3 (data_out[3]),
.\intf.ready_0 (ready[0]),
.\intf.ready_1 (ready[1]),
.\intf.ready_2 (ready[2]),
.\intf.ready_3 (ready[3]),
.\intf.read_0 (read[0]),
.\intf.read_1 (read[1]),
.\intf.read_2 (read[2]),
.\intf.read_3 (read[3]),
.\intf.mem_data (mem_data),
.\intf.mem_add (mem_add),
.\intf.reset (reset),
.\intf.mem_en (mem_en),
.\intf.mem_rd_wr (mem_rd_wr)
);
switch switch1 (.clk (clock),
.reset (reset),
.data_status (data_status),
.data (data_in),
.port0 (data_out[0]),
.port1 (data_out[1]),
.port2 (data_out[2]),
.port3 (data_out[3]),
.ready_0 (ready[0]),
.ready_1 (ready[1]),
.ready_2 (ready[2]),
.ready_3 (ready[3]),
.read_0 (read[0]),
.read_1 (read[1]),
.read_2 (read[2]),
.read_3 (read[3]),
.mem_en (mem_en),
.mem_rd_wr (mem_rd_wr),
.mem_add (mem_add),
.mem_data (mem_data));
initial begin
clock = 0;
forever begin
#5 clock = !clock;
end
end
endmodule //top
Top level module containts the design and testbench instance. Top module also contains clock generator. There is no need to instantiate the top module.
Testbench and dut instances are connected using wires.
CODE: top.v
module top();
//Declare clock signal
reg clock;
//Signals for Assertion and to view the class proprties in Waveform viewer
wire data_status;
wire [7:0] data_in;
wire [7:0] data_out[0:3];
wire [3:0] ready;
wire [3:0] read;
wire [7:0] mem_data;
wire [1:0] mem_add;
wire reset;
wire mem_en;
wire mem_rd_wr;
wire SystemClock ;
assign SystemClock = clock;
main tb ( .SystemClock (SystemClock),
.\intf.clk (clock),
.\intf.data_status (data_status),
.\intf.data_in (data_in),
.\intf.data_out_0 (data_out[0]),
.\intf.data_out_1 (data_out[1]),
.\intf.data_out_2 (data_out[2]),
.\intf.data_out_3 (data_out[3]),
.\intf.ready_0 (ready[0]),
.\intf.ready_1 (ready[1]),
.\intf.ready_2 (ready[2]),
.\intf.ready_3 (ready[3]),
.\intf.read_0 (read[0]),
.\intf.read_1 (read[1]),
.\intf.read_2 (read[2]),
.\intf.read_3 (read[3]),
.\intf.mem_data (mem_data),
.\intf.mem_add (mem_add),
.\intf.reset (reset),
.\intf.mem_en (mem_en),
.\intf.mem_rd_wr (mem_rd_wr)
);
switch switch1 (.clk (clock),
.reset (reset),
.data_status (data_status),
.data (data_in),
.port0 (data_out[0]),
.port1 (data_out[1]),
.port2 (data_out[2]),
.port3 (data_out[3]),
.ready_0 (ready[0]),
.ready_1 (ready[1]),
.ready_2 (ready[2]),
.ready_3 (ready[3]),
.read_0 (read[0]),
.read_1 (read[1]),
.read_2 (read[2]),
.read_3 (read[3]),
.mem_en (mem_en),
.mem_rd_wr (mem_rd_wr),
.mem_add (mem_add),
.mem_data (mem_data));
initial begin
clock = 0;
forever begin
#5 clock = !clock;
end
end
endmodule //top
Index
Introduction
Rtl
Top
Interface
Program Block
Environment
Packet
Configuration
Driver
Reciever
Scoreboard
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Introduction
Rtl
Top
Interface
Program Block
Environment
Packet
Configuration
Driver
Reciever
Scoreboard
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!