OpenVera can communicate to HDL in the following ways.
# Interface Declaration
# Interface Signal Connection
# Virtual Port Signal Connection
# signal_connect() System Function
# Referencing Signals
# Retrieving Signal Properties
# HDL Tasks
Interface Declaration :
The interface specification is used to group Vera signals by clock domain. Each interface may include, at most, one input signal of type CLOCK. The non-clock signals defined in an interface are sampled and driven on the edges of this clock. If an input signal of type CLOCK is not designated, then the interface signals are synchronized using SystemClock.
These are examples of signal declarations with various signal types:
A Vera interface signal can be connected to any user-specified HDL signal in a design using the hdl_node option.
EXAMPLE : hdl_node hdl_nodeCLOCK "hdl_path";
Blocking And Non-Blocking Drives:
Blocking drives suspend Vera execution until the statement completes. Note that the clock edge (NHOLD or PHOLD) that the drive signal is associated with is used for counting synchronized edges during suspension. Once the statement completes, Vera execution resumes.Non-blocking drives schedule the drive at a future synchronized edge and Vera execution continues. When the specified synchronized edge occurs, the drive is executed.
EXAMPLE : Blocking and Nonblocking @2 ram_bus.data = 1; // blocking drive
a = b;
@2 ram_bus.data <= 1; // non-blocking drive
a = b;