| |||
|---|---|---|---|
|
|
||
TOP
Verification Environment:
This is simple verification environment.
It has, packet, Packet generator, Driver, Scoreboard, Receiver, Coverage and Config driver components.
Top Module:
Top module contains the instance of the Dut and verification environment.
It also has the clock generator. For more information about clock generation, go through TB_CONCEPTS in this website.
Creat an Interface and make an instance of the interface file.
Connect the interface instance to dut.
Creat an instance of the program block. Program block containg all the verification component.
CODE: top
module top();
//Declare clock signal
reg clock;
//Signals for Assertion and to view the class proprties in Waveform viewer
reg pkt_status;
wire data_status;
wire [7:0] data_in;
wire [3:0][7:0] data_out;
wire [3:0] ready;
wire [3:0] read;
wire [7:0] mem_data;
wire [1:0] mem_add;
wire reset;
wire mem_en;
wire mem_rd_wr;
reg SystemClock ;
assign SystemClock = clock;
tb vshell ( .SystemClock (SystemClock),
.\intf.clk (clock),
.\intf.data_status (data_status),
.\intf.data_in (data_in),
.\intf.data_out_0 (data_out[0]),
.\intf.data_out_1 (data_out[1]),
.\intf.data_out_2 (data_out[2]),
.\intf.data_out_3 (data_out[3]),
.\intf.ready_0 (ready[0]),
.\intf.ready_1 (ready[1]),
.\intf.ready_2 (ready[2]),
.\intf.ready_3 (ready[3]),
.\intf.read_0 (read[0]),
.\intf.read_1 (read[1]),
.\intf.read_2 (read[2]),
.\intf.read_3 (read[3]),
.\intf.mem_data (mem_data),
.\intf.mem_add (mem_add),
.\intf.reset (reset),
.\intf.mem_en (mem_en),
.\intf.mem_rd_wr (mem_rd_wr)
);
switch switch1 (.clk (clock),
.reset (reset),
.data_status (data_status),
.data (data_in),
.port0 (data_out[0]),
.port1 (data_out[1]),
.port2 (data_out[2]),
.port3 (data_out[3]),
.ready_0 (ready[0]),
.ready_1 (ready[1]),
.ready_2 (ready[2]),
.ready_3 (ready[3]),
.read_0 (read[0]),
.read_1 (read[1]),
.read_2 (read[2]),
.read_3 (read[3]),
.mem_en (mem_en),
.mem_rd_wr (mem_rd_wr),
.mem_add (mem_add),
.mem_data (mem_data));
initial begin
//If you are using always for clock generation, take care not have edge on time 0
clock = 0;
forever begin
#5 clock = !clock;
end
end
endmodule //top
Verification Environment:
This is simple verification environment.
It has, packet, Packet generator, Driver, Scoreboard, Receiver, Coverage and Config driver components.
Top Module:
Top module contains the instance of the Dut and verification environment.
It also has the clock generator. For more information about clock generation, go through TB_CONCEPTS in this website.
Creat an Interface and make an instance of the interface file.
Connect the interface instance to dut.
Creat an instance of the program block. Program block containg all the verification component.
CODE: top
module top();
//Declare clock signal
reg clock;
//Signals for Assertion and to view the class proprties in Waveform viewer
reg pkt_status;
wire data_status;
wire [7:0] data_in;
wire [3:0][7:0] data_out;
wire [3:0] ready;
wire [3:0] read;
wire [7:0] mem_data;
wire [1:0] mem_add;
wire reset;
wire mem_en;
wire mem_rd_wr;
reg SystemClock ;
assign SystemClock = clock;
tb vshell ( .SystemClock (SystemClock),
.\intf.clk (clock),
.\intf.data_status (data_status),
.\intf.data_in (data_in),
.\intf.data_out_0 (data_out[0]),
.\intf.data_out_1 (data_out[1]),
.\intf.data_out_2 (data_out[2]),
.\intf.data_out_3 (data_out[3]),
.\intf.ready_0 (ready[0]),
.\intf.ready_1 (ready[1]),
.\intf.ready_2 (ready[2]),
.\intf.ready_3 (ready[3]),
.\intf.read_0 (read[0]),
.\intf.read_1 (read[1]),
.\intf.read_2 (read[2]),
.\intf.read_3 (read[3]),
.\intf.mem_data (mem_data),
.\intf.mem_add (mem_add),
.\intf.reset (reset),
.\intf.mem_en (mem_en),
.\intf.mem_rd_wr (mem_rd_wr)
);
switch switch1 (.clk (clock),
.reset (reset),
.data_status (data_status),
.data (data_in),
.port0 (data_out[0]),
.port1 (data_out[1]),
.port2 (data_out[2]),
.port3 (data_out[3]),
.ready_0 (ready[0]),
.ready_1 (ready[1]),
.ready_2 (ready[2]),
.ready_3 (ready[3]),
.read_0 (read[0]),
.read_1 (read[1]),
.read_2 (read[2]),
.read_3 (read[3]),
.mem_en (mem_en),
.mem_rd_wr (mem_rd_wr),
.mem_add (mem_add),
.mem_data (mem_data));
initial begin
//If you are using always for clock generation, take care not have edge on time 0
clock = 0;
forever begin
#5 clock = !clock;
end
end
endmodule //top
Index
Dut Specification
Rtl
Top
Interface
Packet
Packet Generator
Cfg Driver
Driver
Reciever
Scoreboard
Env
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Dut Specification
Rtl
Top
Interface
Packet
Packet Generator
Cfg Driver
Driver
Reciever
Scoreboard
Env
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!