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UVM Tutorial
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Easy Labs : SV
Easy Labs : UVM
Easy Labs : OVM
Easy Labs : VMM
AVM Switch TB
VMM Ethernet sample
Verilog
Verification
Verilog Switch TB
Basic Constructs
OpenVera
Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
TEST YOUR UVM OVM SKILLS
(Q
i
40)What
o
e
are
i
the
o
differences
q
between
r
e
vmm
i
and
o
q
j
ovm/uvm
r
e
?
(Q
i
41)What
o
e
is
i
the
o
advantage
q
of
r
e
uvm
i
agent
o
q
j
?
(Q
i
42)How
o
e
multiple
i
set_config_*
o
are
q
resolved
r
e
at
i
same
o
q
j
hierarchy
r
e
level
i
and
o
at
q
different hierarchy
z
levels
u
y
?
(Q
i
43)Is
o
e
it
i
possible
o
to
q
connect
r
e
multiple
i
drivers
o
q
j
to
r
e
one
i
sequencers
o
?
q
if yes,
z
then
u
y
how
e
o
?
(Q
i
44)What
o
e
is
i
the
o
difference
q
between
r
e
factory
i
and
o
q
j
callbacks
r
e
?
www.testbench.in
(Q
i
45)Explain
o
e
the
i
mechanism
o
involved
q
in
r
e
TLM
i
ports.
(Q
i
46)Why
o
e
TLM
i
fifo
o
is
q
used
r
e
?
(Q
i
47)How
o
e
to
i
add
o
a
q
user
r
e
defined
i
phase
o
q
j
?
(Q
i
48)What
o
e
are
i
the
o
ways
q
to
r
e
get
i
the
o
q
j
configuration
r
e
information
i
inside
o
component
q
?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
49)Is
o
e
it
i
possible
o
to
q
use
r
e
get_config_obj
i
inside
o
q
j
a
r
e
sequence
i
class?
o
www.testbench.in
(Q
i
50)What
o
e
is
i
the
o
difference
q
between
r
e
create
i
and
o
q
j
new
r
e
method
i
?
(Q
i
51)What
o
e
is
i
virtual
o
sequencer
q
?
r
e
Explain
i
by
o
q
j
writing
r
e
example.
(Q
i
52)How
o
e
a
i
sequence
o
is
q
started
r
e
?
(Q
i
53)Explain
o
e
end
i
of
o
test
q
mechanism.
r
e
(Q
i
54)When/how
o
e
the
i
stop()
o
method
q
is
r
e
called
i
?
www.testbench.in
(Q
i
55)What
o
e
is
i
port/import/export
o
?
(Q
i
56)Which
o
e
phase
i
is
o
top
q
down,
r
e
and
i
which
o
q
j
phase
r
e
is
i
bottom
o
up?
(Q
i
57)In
o
e
which
i
phase
o
method,
q
super
r
e
method
i
is
o
q
j
required
r
e
to
i
call.
o
q
What if
z
the
u
y
super
e
o
is
z
x
not called ?
(Q
i
58)Explain
o
e
the
i
different
o
phases
q
and
r
e
what
i
is
o
q
j
their
r
e
purpose.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
59)How
o
e
to
i
use
o
factory
q
override
r
e
a
i
sequence
o
q
j
?
r
e
www.testbench.in
(Q
i
60)Explain
o
e
how
i
scoreboard
o
is
q
implemented.
r
e
(Q
i
61)What
o
e
is
i
the
o
use
q
of
r
e
subscriber
i
?
(Q
i
62)Explain
o
e
about
i
run_test().
(Q
i
63)How
o
e
interface
i
is
o
passed
q
to
r
e
component.
(Q
i
64)What
o
e
is
i
the
o
different
q
b/w
r
e
active
i
agent
o
q
j
and
r
e
passive
i
agent
o
?
www.testbench.in
(Q
i
65)Explain
o
e
how
i
a
o
interrupt
q
sequence
r
e
is
i
implemented.
(Q
i
66)Explain
o
e
how
i
layered
o
sequencers
q
are
r
e
implemented.
(Q
i
67)How
o
e
to
i
change
o
the
q
verbosity
r
e
level
i
of
o
q
j
log
r
e
messages
i
from
o
command
q
line ?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
68)How
o
e
to
i
set
o
verbosity
q
level
r
e
to
i
one
o
q
j
particular
r
e
component
i
?
(Q
i
69)How
o
e
to
i
fill
o
the
q
gap
r
e
b/w
i
different
o
q
j
objections?
www.testbench.in
(Q
i
70)What
o
e
is
i
the
o
use
q
of
r
e
uvm_event
i
?
(Q
i
71)How
o
e
to
i
connect
o
multiple
q
sequencers
r
e
to
i
one
o
q
j
driver
r
e
?
(Q
i
72)What
o
e
is
i
returned
o
by
q
get_type_name()?
(Q
i
73)How
o
e
to
i
use
o
set_config_*
q
for
r
e
setting
i
variables
o
q
j
of
r
e
sequence
i
?
(Q
i
74)For
o
e
debugging
i
purpose,
o
how
q
to
r
e
print
i
messages
o
q
j
that
r
e
indicates
i
the
o
components
q
phase ?
www.testbench.in
(Q
i
75)What
o
e
is
i
the
o
disadvantage
q
if
r
e
sequence
i
is
o
q
j
registerd
r
e
to
i
sequencer
o
using
q
utility macros
z
?
u
y
e
o
If
z
x
sequence is not registered with sequencer, then how to invoke the sequence execution ?
(Q
i
76)What
o
e
is
i
the
o
use
q
of
r
e
uvm_create_random_seed
i
?
(Q
i
77)What
o
e
is
i
the
o
difference
q
b/w
r
e
starting
i
a
o
q
j
sequence
r
e
using
i
default_sequence
o
and
q
sequence.start() method.
z
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
78)I
o
e
don~Rt
i
want
o
to
q
register
r
e
a
i
sequence
o
q
j
to
r
e
sequencer.
i
What
o
is
q
the alternate
z
macro
u
y
to
e
o
uvm_sequence_utils()
z
x
macro ?
(Q
i
79)Explain
o
e
how
i
UVM
o
callbacks
q
work
r
e
?
www.testbench.in
(Q
i
80)
o
e
What
i
is
o
the
q
difference
r
e
b/w
i
m_sequencer
o
q
j
and
r
e
p_sequencer
i
?