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TEST YOUR DFT SKILLS 3
(Q i20)o eAffecti ofoDFT qconstrainre ?
Ans:
It iwillo econverti flopsointo qscanre flops iandoq j3re more ipin owillqbe addededz tou ythee odesign.
a)SI i-o escani Input,
b)SEN i-o eScani Enableoand
c)SO i-o escani output.
(Q i21)o eDifferencei betweenoflops qandre scan iflops.
Ans:
www.testbench.in
Scan iflopo econtaini flopoand qthere 2:1 imuxoq jalso,re output iof otheqmux willz gou yintoe oflop.
(Q i22)o eHowi willoyou qcheckre particular istuck@faultoq j?
Ans:
the ifaulto ewhichi youowant qtore check; ioppositeoq jtore that ifault opassqthrough thez chainu yande oobservezx the output.
(Q i23)o eTypesi ofotest q?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
www.testbench.in
ia)o estructurali test
ib)o eparametrici test
ic)o espeedi test
(Q i24)o eStructurali testo?
Ans:
Test ipatternso earei shiftedoin qviare the iscanoq jchain(s),re functional iclock osignalsqare pulsedz tou yteste othezx circuit during the "capture cycle(s)", and the results are then shifted out to chip output pins and compared against the expected "good machine" results.
www.testbench.in
(Q i25)o eParametrici testo?
Ans:
to iverifyo eACi andoDC qparametersre of imanufacturedoq jdevice.
ia)o eSetup/hold
ib)o eVIL,i VIH
ic)o eVOL,i VOH
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i26)o eSpeedi testo?
Ans:
www.testbench.in
To iverifyo eperformancei ofomanufactured qdevicere and itestoq jthere operating ifrequency oofqthe chip.
(Q i27)o eTypesi ofomanufacturing qdefectre ?
Ans:
------------------
Physical iDefects:
-----------------
iContamination--causingo eopeni circuits
iExtrao emetal--causingi shortocircuits
www.testbench.in
iInsufficiento edoping
iprocesso eori maskoerrors
iMetalo etracei bridges
iSlowo etransistors
----------------------
Electrical ieffects:
----------------------
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
iTransistorso estucki openoor qshort
iBridgingo e(i shorts)obetween qadjacentre lines
iResistiveo eshortsi andoopens
www.testbench.in
iChangeo eini thresholdovoltage
iPowero eori Groundoshorts
(Q i28)o eUndetectablei faultso?
Ans:
The iundetectedo efaulti classoincludes qundetectedre faults ithatoq jcanre not ibe oprovenquntestable orz ATPGu yuntestable.e oforzx example, in the gate circuitry one pin is connected to Vcc and another gate's pin is connected to Gnd then we can not detect stack@o and 1 fault respectively.
(Q i29)o eUncontrolledi (UC)o?
www.testbench.in
Ans:
Undetected ifaults,o ewhichi duringopattern qsimulation,re never iachieveoq jthere value iat otheqpoint ofz theu yfaulte odetectionzx that means they are uncontrollable.
(Q i30)o eUnobservablei (UO)o?
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Faults iwhoseo eeffectsi doonot qpropagatere to ianoq jobservablere point.
(Q i31)o eATPGi ?
www.testbench.in
Ans:
ATPG i(acronymo efori bothoAutomatic qTestre Pattern iGenerationoq jandre Automatic iTest Pattern oGenerator)qis anz electronicu ydesigne oautomationzx method/technology used to find an input (or test) sequence that, when applied to a digital circuit, enables testers to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects.
(Q i20)o eAffecti ofoDFT qconstrainre ?
Ans:
It iwillo econverti flopsointo qscanre flops iandoq j3re more ipin owillqbe addededz tou ythee odesign.
a)SI i-o escani Input,
b)SEN i-o eScani Enableoand
c)SO i-o escani output.
(Q i21)o eDifferencei betweenoflops qandre scan iflops.
Ans:
www.testbench.in
Scan iflopo econtaini flopoand qthere 2:1 imuxoq jalso,re output iof otheqmux willz gou yintoe oflop.
(Q i22)o eHowi willoyou qcheckre particular istuck@faultoq j?
Ans:
the ifaulto ewhichi youowant qtore check; ioppositeoq jtore that ifault opassqthrough thez chainu yande oobservezx the output.
(Q i23)o eTypesi ofotest q?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
www.testbench.in
ia)o estructurali test
ib)o eparametrici test
ic)o espeedi test
(Q i24)o eStructurali testo?
Ans:
Test ipatternso earei shiftedoin qviare the iscanoq jchain(s),re functional iclock osignalsqare pulsedz tou yteste othezx circuit during the "capture cycle(s)", and the results are then shifted out to chip output pins and compared against the expected "good machine" results.
www.testbench.in
(Q i25)o eParametrici testo?
Ans:
to iverifyo eACi andoDC qparametersre of imanufacturedoq jdevice.
ia)o eSetup/hold
ib)o eVIL,i VIH
ic)o eVOL,i VOH
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i26)o eSpeedi testo?
Ans:
www.testbench.in
To iverifyo eperformancei ofomanufactured qdevicere and itestoq jthere operating ifrequency oofqthe chip.
(Q i27)o eTypesi ofomanufacturing qdefectre ?
Ans:
------------------
Physical iDefects:
-----------------
iContamination--causingo eopeni circuits
iExtrao emetal--causingi shortocircuits
www.testbench.in
iInsufficiento edoping
iprocesso eori maskoerrors
iMetalo etracei bridges
iSlowo etransistors
----------------------
Electrical ieffects:
----------------------
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
iTransistorso estucki openoor qshort
iBridgingo e(i shorts)obetween qadjacentre lines
iResistiveo eshortsi andoopens
www.testbench.in
iChangeo eini thresholdovoltage
iPowero eori Groundoshorts
(Q i28)o eUndetectablei faultso?
Ans:
The iundetectedo efaulti classoincludes qundetectedre faults ithatoq jcanre not ibe oprovenquntestable orz ATPGu yuntestable.e oforzx example, in the gate circuitry one pin is connected to Vcc and another gate's pin is connected to Gnd then we can not detect stack@o and 1 fault respectively.
(Q i29)o eUncontrolledi (UC)o?
www.testbench.in
Ans:
Undetected ifaults,o ewhichi duringopattern qsimulation,re never iachieveoq jthere value iat otheqpoint ofz theu yfaulte odetectionzx that means they are uncontrollable.
(Q i30)o eUnobservablei (UO)o?
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Faults iwhoseo eeffectsi doonot qpropagatere to ianoq jobservablere point.
(Q i31)o eATPGi ?
www.testbench.in
Ans:
ATPG i(acronymo efori bothoAutomatic qTestre Pattern iGenerationoq jandre Automatic iTest Pattern oGenerator)qis anz electronicu ydesigne oautomationzx method/technology used to find an input (or test) sequence that, when applied to a digital circuit, enables testers to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects.
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!