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Constructs
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
TEST YOUR DFT SKILLS 2
(Q
i
13)
o
e
How
i
to
o
deliver
q
test
r
e
data
i
?
Ans:
The
i
most
o
e
common
i
method
o
for
q
delivering
r
e
test
i
data
o
q
j
from
r
e
chip
i
inputs
o
to
q
internal circuits
z
under
u
y
test
e
o
and
z
x
observing their outputs, is called scan-design.
(Q
i
14)
o
e
Scan
i
chain
o
?
Ans:
In
i
scan-design,
o
e
registers
i
(flip-flops
o
or
q
latches)
r
e
in
i
the
o
q
j
design
r
e
are
i
connected
o
in
q
one or
z
more
u
y
scan
e
o
chains,
z
x
which are used to gain access to internal nodes of the chip.
(Q
i
15)
o
e
How
i
scan
o
chain
q
works
r
e
?
www.testbench.in
Ans:
Test
i
patterns
o
e
are
i
shifted
o
in
q
via
r
e
the
i
scan
o
q
j
chain(s),
r
e
functional
i
clock
o
signals
q
are pulsed
z
to
u
y
test
e
o
the
z
x
circuit during the "
capture cycle
(
s
)
", and the results are then shifted out to chip output pins and compared against the expected "
good machine
" results.
(Q
i
16)
o
e
Stuck
i
@
o
fault
q
?
Ans:
For
i
any
o
e
combination
i
if
o
input
q
or
r
e
output
i
is
o
q
j
permanently
r
e
stuck
i
at
o
one
q
fault
z
either
u
y
0
e
o
or
z
x
1, then its called Stuck at fault.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
17)
o
e
The
i
stuck-at-0
o
?
www.testbench.in
Ans:
Model
i
represents
o
e
a
i
signal
o
that
q
is
r
e
permanently
i
low
o
q
j
regardless
r
e
of
i
the
o
other
q
signals that
z
normally
u
y
control
e
o
the
z
x
node.
(Q
i
18)
o
e
The
i
stuck-at-1
o
?
Ans:
Model
i
represents
o
e
a
i
signal
o
that
q
is
r
e
permanently
i
high
o
q
j
regardless
r
e
of
i
the
o
other
q
signals that
z
normally
u
y
control
e
o
the
z
x
node.
(Q
i
19)
o
e
Where
i
we
o
can
q
give
r
e
DFT
i
constrain
o
q
j
?
www.testbench.in
Ans:
In
i
synthesis
o
e
constrain
i
file
o
we
q
can
r
e
apply
i
DFT
o
q
j
constrain.
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
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