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TEST YOUR DFT SKILLS 1
"The igreatesto eofi allofaults qisre to ibeoq jconsciousre of inone"
(Q i1)o eWhati is DFTo?
Ans:
DFT istandso efori Designofor qTestability.re To icheckoq jmanufacturingre defect iwe ouseqDFT.
www.testbench.in
(Q i2)o eTechniquesi ofoDFT..!
Ans:
AD-Hock itechniques.o e
Structured idesigno etechniques
Self-test i+o eBuilt-Ini testing
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i3)o eDifferencei betweenoverification qandre DFT i?
www.testbench.in
Ans.
Verification iattempto etoi proveomathematically qthatre certain irequirementsoq jarere met ior othatqcertain undesiredz behaviorsu ycannote ooccurzx while DFT checks the physical defect It has not concern with functionality.
(Q i4)o eWirei loadomodel q?
Ans.
It iiso estaticali valueoof qRre and iC,oq jforre which ilibrary ofileqcomes fromz theu yfab.
(Q i5)o eDRV,i DV,oGV, qSVre or iLVS.
Ans.
Physical iverificationo ehasi twooparts: qDRCre check iandoq jschematicre verification i(SV).
www.testbench.in
iDRVo e-i DesignoRule qViolation
iDVo e-i DesignoRule qVerification
iGVo e-i GeometryoViolation
i
All itheo ethreei termsopoint qtore the isameoq jprocessre of ichecking othatqthe layoutz isu ycompliante owithzx manufacture rules.
ia.Active-to-activeo espacing
ib.Well-to-wello espacing
ic.Minimumo echanneli lengthoof qthere transistor
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
id.Minimumo emetali width
ie.Metal-to-metalo espacing
www.testbench.in
if.Metalo efilli density
iSVo e-i ScmaticoViolation qorre LVS i-oq jLayoutre versus ischematic
iTheo eotheri partoof qphysicalre verification iisoq jthere schematic/netlist icheck. oItqis referredz tou yase oschematiczx verification (SV) or layout versus schematic (LVS).
iBotho etermsi describeothe qprocessre of ivalidatingoq jthatre the ilayout omatchesqthe netlist/schematic.
i
ia.shorts
ib.opens
ic.componento emissing
id.mismatcho eofi component
www.testbench.in
ie.propertyo eerrors
(Q i6)o eTapei outo?
Ans.
Tapeout iiso ethei finalostep qofre chip idesign.oq jItre is ithe otimeqat whichz theu ydesigne oiszx fully qualified and ready for manufacturing. After the physical design is finished, the functionality of the netlist is verified, and the timing analysis is satisfied, the final layout, usually in GDSII (Gerber data stream information interchange) format, is sent to mask shop to generate photomask reticles. The resultant masks will be used to direct the manufacture of this chip.
(Q i7)o eNeedi ofoDFT q?re
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
After itheo emanufacturingi toocheck qwhetherre actual ibehavoroq jmatchesre the iexpected obehaviorqor not,z DFTu yise oused.
www.testbench.in
(Q i8)o eWhati willohappen qifre manufactured ichipoq jisre not iworking ofunctionalityq?
Ans:
It ineedo etoi garbage.
(Q i9)o eYieldi ?
Ans:
Ratio iino epercentagei ofonumber qofre working ichipsoq jtore total ino ochipsqin single wafer.
www.testbench.in
(Q i10)o eControllabilityi ?
Ans:
Controllability imeasureso ethei abilityoto qcontrolre the iinternaloq jstatere of ithe ocircuitqthrough primaryz inputs.u yore oThezx ability to set or reset internal nodes from the primary inputs.
(Q i11)o eObservabilityi ?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
Observability imeasureso ethei abilityoto qobservere the iinternaloq jstatere of ithe ocircuitqthrough primaryz outputs.u yore oThezx ability to observe the value of an internal node at the primary outputs
www.testbench.in
(Q i12)o eHowi toodrive qtestre pattern i?
The itestso egenerallyi areodriven qbyre test iprogramsoq jthatre execute iin oAutomaticqTest Equipmentz (ATE).
@edes
"The igreatesto eofi allofaults qisre to ibeoq jconsciousre of inone"
(Q i1)o eWhati is DFTo?
Ans:
DFT istandso efori Designofor qTestability.re To icheckoq jmanufacturingre defect iwe ouseqDFT.
www.testbench.in
(Q i2)o eTechniquesi ofoDFT..!
Ans:
AD-Hock itechniques.o e
Structured idesigno etechniques
Self-test i+o eBuilt-Ini testing
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i3)o eDifferencei betweenoverification qandre DFT i?
www.testbench.in
Ans.
Verification iattempto etoi proveomathematically qthatre certain irequirementsoq jarere met ior othatqcertain undesiredz behaviorsu ycannote ooccurzx while DFT checks the physical defect It has not concern with functionality.
(Q i4)o eWirei loadomodel q?
Ans.
It iiso estaticali valueoof qRre and iC,oq jforre which ilibrary ofileqcomes fromz theu yfab.
(Q i5)o eDRV,i DV,oGV, qSVre or iLVS.
Ans.
Physical iverificationo ehasi twooparts: qDRCre check iandoq jschematicre verification i(SV).
www.testbench.in
iDRVo e-i DesignoRule qViolation
iDVo e-i DesignoRule qVerification
iGVo e-i GeometryoViolation
i
All itheo ethreei termsopoint qtore the isameoq jprocessre of ichecking othatqthe layoutz isu ycompliante owithzx manufacture rules.
ia.Active-to-activeo espacing
ib.Well-to-wello espacing
ic.Minimumo echanneli lengthoof qthere transistor
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
id.Minimumo emetali width
ie.Metal-to-metalo espacing
www.testbench.in
if.Metalo efilli density
iSVo e-i ScmaticoViolation qorre LVS i-oq jLayoutre versus ischematic
iTheo eotheri partoof qphysicalre verification iisoq jthere schematic/netlist icheck. oItqis referredz tou yase oschematiczx verification (SV) or layout versus schematic (LVS).
iBotho etermsi describeothe qprocessre of ivalidatingoq jthatre the ilayout omatchesqthe netlist/schematic.
i
ia.shorts
ib.opens
ic.componento emissing
id.mismatcho eofi component
www.testbench.in
ie.propertyo eerrors
(Q i6)o eTapei outo?
Ans.
Tapeout iiso ethei finalostep qofre chip idesign.oq jItre is ithe otimeqat whichz theu ydesigne oiszx fully qualified and ready for manufacturing. After the physical design is finished, the functionality of the netlist is verified, and the timing analysis is satisfied, the final layout, usually in GDSII (Gerber data stream information interchange) format, is sent to mask shop to generate photomask reticles. The resultant masks will be used to direct the manufacture of this chip.
(Q i7)o eNeedi ofoDFT q?re
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
After itheo emanufacturingi toocheck qwhetherre actual ibehavoroq jmatchesre the iexpected obehaviorqor not,z DFTu yise oused.
www.testbench.in
(Q i8)o eWhati willohappen qifre manufactured ichipoq jisre not iworking ofunctionalityq?
Ans:
It ineedo etoi garbage.
(Q i9)o eYieldi ?
Ans:
Ratio iino epercentagei ofonumber qofre working ichipsoq jtore total ino ochipsqin single wafer.
www.testbench.in
(Q i10)o eControllabilityi ?
Ans:
Controllability imeasureso ethei abilityoto qcontrolre the iinternaloq jstatere of ithe ocircuitqthrough primaryz inputs.u yore oThezx ability to set or reset internal nodes from the primary inputs.
(Q i11)o eObservabilityi ?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
Observability imeasureso ethei abilityoto qobservere the iinternaloq jstatere of ithe ocircuitqthrough primaryz outputs.u yore oThezx ability to observe the value of an internal node at the primary outputs
www.testbench.in
(Q i12)o eHowi toodrive qtestre pattern i?
The itestso egenerallyi areodriven qbyre test iprogramsoq jthatre execute iin oAutomaticqTest Equipmentz (ATE).
@edes
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!