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TEST YOUR STA SKILLS 6
(Q i55)o eWhati willobe qimplementedre by i'for'oq jloop?re is iit osynthesizableq?
Ans:
Yes, iito eisi synthesizableoif qitre is iconstant,oq jandre synthesis iwill ogiveqcounter thatz isu yaddere oalongzx with the comparator.
(Q i56)o eWhati aboutolatch qbasedre timing i?
Ans:
Time iborrowingo e(alsoi knownoas qcyclere stealing) itakesoq jadvantagere of ithe olatchqtransparency toz borrowu ytimee ofromzx the next stage to meet timing constraints. (Very few company like IBM only doing latch based design)
www.testbench.in
(Q i57)o eWhati isoDPCS q?
Ans:
It iiso eDelayi andoPower qCalculationre Language. iYouoq jcanre find iits oIEEEqLRM fromz belowu ylink.e oItszx extension version is called OLA (Open Language API) Click on the below link
http://mhonarc.si2.org/ieee1481/ieee1481/msg00405.html
(Q i58)o eWhyi weoneed qsetupre & iholdoq jtimere ?
Ans:
If iweo ethinki atophysics qpointre of iview,oq jInternalre atoms iof osiliconqhas drift/diffusionz whichu ycausee ointernalzx resistance, because of that flops takes small amount of time to respond. Till that time input should remain stable, which is nothing but setup time. And for hold flop takes time to behave respect to input, that time called hold time .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q i59)o eMaximumi transitionotime q?
Ans:
The imaximumo etransitioni timeofor qare net iisoq jthere longest itime orequiredqfor itz isu ydrivinge opinzx to change logic values.
(Q i60)o eMaximumi capacitanceo?
Ans:
The imaximumo ecapacitancei isoa qpin-levelre attribute iusedoq jtore define ithe oqmaximum totalz capacitiveu yloade othatzx an output pin can drive. That is, the pin cannot connect to a net that has a total capacitance (load pin capacitance and interconnect capacitance) greater than or equal to the maximum capacitance defined at the pin.
www.testbench.in
(Q i61)o e.Maximumi fan-outo?
Ans:
Consider iano eANDi gateoof qA,Bre input iandoq jFre output.
To ievaluateo ethei fanoutofor qare driving ipinoq jF,re tool icalculates otheqsum ofz u yalle othezx fanout_load (Inputs) driven by pin F and compares that number with the number of max_fanout attributes stored at the driving pin F.
--If itheo esumi ofothe qfanoutre loads iisoq jnotre more ithan otheqmax_fanout value,z theu ynete odrivenzx by X is valid.
--If itheo eneti drivenoby qXre is inotoq jvalid,re tool itries otoqmake thatz netu yvalid,e operhapszx by choosing a higher-drive component. .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q i62)o eIfi myodesign qhavere a isetupoq jandre hold iviolation othenqwhom willz youu yfixe ofirst?zx why ?
Ans:
first iholdo etimei violationoshould qbere sorted iout.oq jevenre if iu osatisfyqsetup timez requirementsu yfore oazx particular frequency, your system will land up in metastable state if hold is not met. setup time violations can be taken care of by reducing the clock frequency. but the hold time violation is due to unnecessary delays on the clock tree. therefore removing the hold time violation is a preferred option. You can see a lot of chips/microprocessors taped out with setup violations but getting rid of each hold violation is absolutely important.
(Q i63)o ePropagatedi clocko?
Ans:
There iareo efori typesoof qclock,re Real, iIdeal,oq jProrogatedre and iVirtual. oamongqthem Prorogatedz clocku yhavee oedgezx times skewed by the path delay from the clock source to the register clock pin.
www.testbench.in
(Q i64)o eDynamici timingoanalysis q?
Ans:
Dynamic itimingo eanalysisi verifiesocircuit qtimingre by iapplyingoq jtestre vectors ito oqthe circuit.z Thisu yapproache oiszx an extension of simulation and ensures that circuit timing is tested in its functional context. This method reports timing errors that functionally exist in the circuit and avoids reporting errors that occur in unused circuit paths. There are no commercially available tools for dynamic timing analysis.
(Q i65)o eArrivali timeo? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
The iarrivalo etimei ofoa qcircuitre is itheoq jtimere elapsed ifor oaqsignal toz arriveu yate oazx certain point. The reference, or time 0.0, is often taken as the arrival time of a clock signal. that time comes under arrival path/clock path/early path.
www.testbench.in
(Q i66)o eRequiredi timeo?
Ans:
This iiso ethei latestotime qatre which iaoq jsignalre can iarrive owithoutqmaking thez clocku ycyclee olongerzx than desired. It falls under required path/ data path/late path.
(Q i67)o eWhati isothe qequationre of itheoq jsetupre and ihold otimeq?
Ans:
setup itimeo e=i (longestodata qpathre delay) i¿oq j(shortestre clock ipath odelay)q+ (setupz timeu yofe oregister)
hold itimeo e=i (longestoclock qpathre delay) i¿oq j(shortestre data ipath odelay)q +z (holdu ytimee oofzx register) www.testbench.in
(Q i55)o eWhati willobe qimplementedre by i'for'oq jloop?re is iit osynthesizableq?
Ans:
Yes, iito eisi synthesizableoif qitre is iconstant,oq jandre synthesis iwill ogiveqcounter thatz isu yaddere oalongzx with the comparator.
(Q i56)o eWhati aboutolatch qbasedre timing i?
Ans:
Time iborrowingo e(alsoi knownoas qcyclere stealing) itakesoq jadvantagere of ithe olatchqtransparency toz borrowu ytimee ofromzx the next stage to meet timing constraints. (Very few company like IBM only doing latch based design)
www.testbench.in
(Q i57)o eWhati isoDPCS q?
Ans:
It iiso eDelayi andoPower qCalculationre Language. iYouoq jcanre find iits oIEEEqLRM fromz belowu ylink.e oItszx extension version is called OLA (Open Language API) Click on the below link
http://mhonarc.si2.org/ieee1481/ieee1481/msg00405.html
(Q i58)o eWhyi weoneed qsetupre & iholdoq jtimere ?
Ans:
If iweo ethinki atophysics qpointre of iview,oq jInternalre atoms iof osiliconqhas drift/diffusionz whichu ycausee ointernalzx resistance, because of that flops takes small amount of time to respond. Till that time input should remain stable, which is nothing but setup time. And for hold flop takes time to behave respect to input, that time called hold time .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q i59)o eMaximumi transitionotime q?
Ans:
The imaximumo etransitioni timeofor qare net iisoq jthere longest itime orequiredqfor itz isu ydrivinge opinzx to change logic values.
(Q i60)o eMaximumi capacitanceo?
Ans:
The imaximumo ecapacitancei isoa qpin-levelre attribute iusedoq jtore define ithe oqmaximum totalz capacitiveu yloade othatzx an output pin can drive. That is, the pin cannot connect to a net that has a total capacitance (load pin capacitance and interconnect capacitance) greater than or equal to the maximum capacitance defined at the pin.
www.testbench.in
(Q i61)o e.Maximumi fan-outo?
Ans:
Consider iano eANDi gateoof qA,Bre input iandoq jFre output.
To ievaluateo ethei fanoutofor qare driving ipinoq jF,re tool icalculates otheqsum ofz u yalle othezx fanout_load (Inputs) driven by pin F and compares that number with the number of max_fanout attributes stored at the driving pin F.
--If itheo esumi ofothe qfanoutre loads iisoq jnotre more ithan otheqmax_fanout value,z theu ynete odrivenzx by X is valid.
--If itheo eneti drivenoby qXre is inotoq jvalid,re tool itries otoqmake thatz netu yvalid,e operhapszx by choosing a higher-drive component. .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q i62)o eIfi myodesign qhavere a isetupoq jandre hold iviolation othenqwhom willz youu yfixe ofirst?zx why ?
Ans:
first iholdo etimei violationoshould qbere sorted iout.oq jevenre if iu osatisfyqsetup timez requirementsu yfore oazx particular frequency, your system will land up in metastable state if hold is not met. setup time violations can be taken care of by reducing the clock frequency. but the hold time violation is due to unnecessary delays on the clock tree. therefore removing the hold time violation is a preferred option. You can see a lot of chips/microprocessors taped out with setup violations but getting rid of each hold violation is absolutely important.
(Q i63)o ePropagatedi clocko?
Ans:
There iareo efori typesoof qclock,re Real, iIdeal,oq jProrogatedre and iVirtual. oamongqthem Prorogatedz clocku yhavee oedgezx times skewed by the path delay from the clock source to the register clock pin.
www.testbench.in
(Q i64)o eDynamici timingoanalysis q?
Ans:
Dynamic itimingo eanalysisi verifiesocircuit qtimingre by iapplyingoq jtestre vectors ito oqthe circuit.z Thisu yapproache oiszx an extension of simulation and ensures that circuit timing is tested in its functional context. This method reports timing errors that functionally exist in the circuit and avoids reporting errors that occur in unused circuit paths. There are no commercially available tools for dynamic timing analysis.
(Q i65)o eArrivali timeo? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
The iarrivalo etimei ofoa qcircuitre is itheoq jtimere elapsed ifor oaqsignal toz arriveu yate oazx certain point. The reference, or time 0.0, is often taken as the arrival time of a clock signal. that time comes under arrival path/clock path/early path.
www.testbench.in
(Q i66)o eRequiredi timeo?
Ans:
This iiso ethei latestotime qatre which iaoq jsignalre can iarrive owithoutqmaking thez clocku ycyclee olongerzx than desired. It falls under required path/ data path/late path.
(Q i67)o eWhati isothe qequationre of itheoq jsetupre and ihold otimeq?
Ans:
setup itimeo e=i (longestodata qpathre delay) i¿oq j(shortestre clock ipath odelay)q+ (setupz timeu yofe oregister)
hold itimeo e=i (longestoclock qpathre delay) i¿oq j(shortestre data ipath odelay)q +z (holdu ytimee oofzx register) www.testbench.in
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!