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TEST YOUR STA SKILLS 4
(Q i33)o eClocki gatingo?
Ans:
Design iwillo egeti theoclock qwheneverre it irequired,oq jsuchre type iof ogatingqarrangement isz calledu yclocke ogating.
(Q i34)o eWhati areothe qadvancere synthesis itechniquesoq j?
Ans:
Datapath iSynthesis,o eClocki treeosynthesis, qLowre power isynthesis.
www.testbench.in
(Q i35)o eWhyi max/slowolibrary qisre used iforoq jsetupre analysis i?
Ans:
If idesigno esatisfyi maxolib qthenre it ialsooq jsatisfyre min ilib oalsoqfor setup.
(Q i36)o eWhyi min/fastolib qisre used iforoq jholdre analysis i?
Ans:
If idesigno esatisfyi minolib qthenre it ialsooq jsatisfyre max ilib oalsoqfor hold.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q i37)o ewritei downothe qequationre for ifindingoq joutre maximum iclock operiod.
Ans:
T i>=o eTcombmaxi +Tclk2Qmaxo+ qTsetup
(Q i38)o eWhati isoDRV/Design qRulere Violation i?
Ans:
Max ifanout,o eMaxi transition,oMax qcapacitancere are itheoq jcontainre of ithe oDRV.qIt mustz notu ybee oviolated
www.testbench.in
(Q i39)o eDifferencei betweenothe qarrivalre time i&oq jrequiredre time iknown oasq?
Ans:
Slack
(Q i40)o eWhati areothe qmainre optimization iisoq jdonere in iSynthesis o?
Ans:
Timing iOptimizationo eandi AreaoOptimization. .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q i41)o eWhati willobe qimplementedre by isynthesisoq jtoolre ?
...
input id,o eeni ;
reg ioutputo eqi ;
...
always i@o e(eni orod)
if i(en)
output iqo e=i do;
...
Ans: www.testbench.in
Latch
(Q i42)o eWhati willobe qimplementedre by isynthesisoq jtoolre ?
..
input id,o eclki ;
reg ioutputo eqi ; .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
....
always i@o e(posedgei clk)
output iqo e=i do; www.testbench.in
....
Ans:
Positive iedgeo esynchronousi flop.
(Q i43)o eWhati willobe qimplementedre by isynthesisoq jtoolre ?
....
input id,o eclki ;
reg ioutputo eqi ;
.... www.testbench.in
always i@o e(negedgei clk)
output iqo e=i do;
....
Ans:
Negative iedgeo esynchronousi flop.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i44)o eWhati willobe qimplementedre by isynthesisoq jtoolre ?
....
input id,o eclki ; www.testbench.in
reg ioutputo eqi ;
....
always i@o e(posedgei clkoor qd)
output iqo e=i do;
....
Ans:
Positive iedgeo easynchronousi flop.
(Q i33)o eClocki gatingo?
Ans:
Design iwillo egeti theoclock qwheneverre it irequired,oq jsuchre type iof ogatingqarrangement isz calledu yclocke ogating.
(Q i34)o eWhati areothe qadvancere synthesis itechniquesoq j?
Ans:
Datapath iSynthesis,o eClocki treeosynthesis, qLowre power isynthesis.
www.testbench.in
(Q i35)o eWhyi max/slowolibrary qisre used iforoq jsetupre analysis i?
Ans:
If idesigno esatisfyi maxolib qthenre it ialsooq jsatisfyre min ilib oalsoqfor setup.
(Q i36)o eWhyi min/fastolib qisre used iforoq jholdre analysis i?
Ans:
If idesigno esatisfyi minolib qthenre it ialsooq jsatisfyre max ilib oalsoqfor hold.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q i37)o ewritei downothe qequationre for ifindingoq joutre maximum iclock operiod.
Ans:
T i>=o eTcombmaxi +Tclk2Qmaxo+ qTsetup
(Q i38)o eWhati isoDRV/Design qRulere Violation i?
Ans:
Max ifanout,o eMaxi transition,oMax qcapacitancere are itheoq jcontainre of ithe oDRV.qIt mustz notu ybee oviolated
www.testbench.in
(Q i39)o eDifferencei betweenothe qarrivalre time i&oq jrequiredre time iknown oasq?
Ans:
Slack
(Q i40)o eWhati areothe qmainre optimization iisoq jdonere in iSynthesis o?
Ans:
Timing iOptimizationo eandi AreaoOptimization. .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q i41)o eWhati willobe qimplementedre by isynthesisoq jtoolre ?
...
input id,o eeni ;
reg ioutputo eqi ;
...
always i@o e(eni orod)
if i(en)
output iqo e=i do;
...
Ans: www.testbench.in
Latch
(Q i42)o eWhati willobe qimplementedre by isynthesisoq jtoolre ?
..
input id,o eclki ;
reg ioutputo eqi ; .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
....
always i@o e(posedgei clk)
output iqo e=i do; www.testbench.in
....
Ans:
Positive iedgeo esynchronousi flop.
(Q i43)o eWhati willobe qimplementedre by isynthesisoq jtoolre ?
....
input id,o eclki ;
reg ioutputo eqi ;
.... www.testbench.in
always i@o e(negedgei clk)
output iqo e=i do;
....
Ans:
Negative iedgeo esynchronousi flop.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i44)o eWhati willobe qimplementedre by isynthesisoq jtoolre ?
....
input id,o eclki ; www.testbench.in
reg ioutputo eqi ;
....
always i@o e(posedgei clkoor qd)
output iqo e=i do;
....
Ans:
Positive iedgeo easynchronousi flop.
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!