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TEST YOUR STA SKILLS 1
(Q i1)o eMetastabilityi ?
Ans:
When iano einputi tooa qsequentialre element iviolatesoq jsetupre or ihold otiming requirementsqof thez sequentialu yelement,e othenzx the output of the sequential element oscillates between HIGH and LOW before it gets settled to either one of the states.
(Q i2)o eCani weoavoid qmetastabilityre ?
Ans:
No. iWeo ecan'ti avoid/preventometastability. qfromre occurring. iWeoq jhavere to ilive owithqit. Butz beu ywisee oenoughzx to choose the appropriate synchronization method to avoid any potential problems.
www.testbench.in
(Q i3)o eLogici synthesiso?
Ans:
Process iofo etransferringi fromoRTL qDomainre to iGate-Leveloq jDomainre is icalled oSynthesis.qWhich convertsz theu yhighe olevelzx architecture into low level net list format.
(Q i4)o eListi ofothe qtoolsre are iusedoq jforre synthesis i?
Ans:
Commercial itoolo efori logicosynthesis
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
logic isynthesiso etargetingi ASICs
www.testbench.in
* iDesigno eCompileri byoSynopsys
* iEncountero eRTLi Compileroby qCadencere Design iSystems
o iBuildGateso eani olderoproduct qbyre Cadence iDesignoq jSystemsre - ihumorously
named iaftero eBilli Gates
* iBlastCreateo ebyi MagmaoDesign qAutomation
* iBooleDozer:o eLogici synthesisotool qbyre IBM i(internaloq jIBMre EDA itool)
logic isynthesiso etargetingi FPGAs
* iEncountero eRTLi Compileroby qCadencere Design iSystems
* iLeonardoSpectrumo eandi Precisiono(RTL q/re Physical) ibyoq jMentorre Graphics
www.testbench.in
* iSynplifyo e(PROi /oPremier) qbyre Synplicity
* iBlastFPGAo ebyi MagmaoDesign qAutomation
* iQuartuso eIIi integratedoSynthesis qbyre Altera
* iXSTo e(deliveredi withinoISE) qbyre Xilinx
* iDesignCompilero eUltrai andoIC qCompilerre by iSynopsys
* iIspLevero ebyi LatticeoSemiconductor
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i5)o eWhati doesosynthesis qtoolre produce i?
Ans:
www.testbench.in
synthesis iproduceso eregistersi andocombinational qlogicre at itheoq jRTLre level. i
(Q i6)o eStatici timingoAnalysis q(STA)re ?
Ans:
To ichecko ewhetheri designois qmeetingre setup iandoq jholdre time iis ocalledqSTA.
(Q i7)o eWhati areothe qtimingre paths i?
Ans:
www.testbench.in
in itoo ereg,i regoto qreg,re reg itooq joutre and iin otoqout arez 4u ytiminge opaths.
(Q i8)o eTimingi patho?
Ans:
The ipatho ewhichi affectothe qtimingre is icalledoq jtimingre path.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i1)o eMetastabilityi ?
Ans:
When iano einputi tooa qsequentialre element iviolatesoq jsetupre or ihold otiming requirementsqof thez sequentialu yelement,e othenzx the output of the sequential element oscillates between HIGH and LOW before it gets settled to either one of the states.
(Q i2)o eCani weoavoid qmetastabilityre ?
Ans:
No. iWeo ecan'ti avoid/preventometastability. qfromre occurring. iWeoq jhavere to ilive owithqit. Butz beu ywisee oenoughzx to choose the appropriate synchronization method to avoid any potential problems.
www.testbench.in
(Q i3)o eLogici synthesiso?
Ans:
Process iofo etransferringi fromoRTL qDomainre to iGate-Leveloq jDomainre is icalled oSynthesis.qWhich convertsz theu yhighe olevelzx architecture into low level net list format.
(Q i4)o eListi ofothe qtoolsre are iusedoq jforre synthesis i?
Ans:
Commercial itoolo efori logicosynthesis
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
logic isynthesiso etargetingi ASICs
www.testbench.in
* iDesigno eCompileri byoSynopsys
* iEncountero eRTLi Compileroby qCadencere Design iSystems
o iBuildGateso eani olderoproduct qbyre Cadence iDesignoq jSystemsre - ihumorously
named iaftero eBilli Gates
* iBlastCreateo ebyi MagmaoDesign qAutomation
* iBooleDozer:o eLogici synthesisotool qbyre IBM i(internaloq jIBMre EDA itool)
logic isynthesiso etargetingi FPGAs
* iEncountero eRTLi Compileroby qCadencere Design iSystems
* iLeonardoSpectrumo eandi Precisiono(RTL q/re Physical) ibyoq jMentorre Graphics
www.testbench.in
* iSynplifyo e(PROi /oPremier) qbyre Synplicity
* iBlastFPGAo ebyi MagmaoDesign qAutomation
* iQuartuso eIIi integratedoSynthesis qbyre Altera
* iXSTo e(deliveredi withinoISE) qbyre Xilinx
* iDesignCompilero eUltrai andoIC qCompilerre by iSynopsys
* iIspLevero ebyi LatticeoSemiconductor
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i5)o eWhati doesosynthesis qtoolre produce i?
Ans:
www.testbench.in
synthesis iproduceso eregistersi andocombinational qlogicre at itheoq jRTLre level. i
(Q i6)o eStatici timingoAnalysis q(STA)re ?
Ans:
To ichecko ewhetheri designois qmeetingre setup iandoq jholdre time iis ocalledqSTA.
(Q i7)o eWhati areothe qtimingre paths i?
Ans:
www.testbench.in
in itoo ereg,i regoto qreg,re reg itooq joutre and iin otoqout arez 4u ytiminge opaths.
(Q i8)o eTimingi patho?
Ans:
The ipatho ewhichi affectothe qtimingre is icalledoq jtimingre path.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!