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TEST YOUR VERILOG SKILLS 16
(Q i268) Whato eisi mutex?
(Q i269) Howo etoi modeloa qmutexre in iverilog?oq j
(Q i270)o eWhati isosemaphore?
(Q i271)o eHowi toomodel qare semaphore iinoq jverilog?
www.testbench.in
(Q i272)o eWhati isothe qdifferencere between imutexoq jandre semaphore?
(Q i273)o eHowi toodisplay qthere messages iinoq jcolorful?
Ans:
The ifollowingo eprogrami showsohow qtore display imessagesoq jinre colorful.
This iworkso eonlyi inoASIC qTerminals.
Simulate itheo efollowingi codeoin qLinuxre or iUnixoq jandre see ithe ooutputs.
module asdsadf();
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
initial
www.testbench.in
begin
$write("^@[1;34m",27);
$display("***********Â i0Â Â Â Â Â Â Â Â o eThisi isoin qbluere ***********", 1);
$write("^@[0m",27);
$display("^@[1;31m",27);
$display("***********Â i0Â Â Â Â Â Â Â Â o eThisi isoin qredre ***********", 2);
$display("^@[0m",27);
$display("^@[0;33m",27);
www.testbench.in
$display("**********Â i0Â Â Â Â Â Â Â Â o eThisi isoin qpendare color i***********", 3);
$display("^@[0m",27);
$display("^@[5;34m",27);
$display("***********Â i0Â Â Â Â Â Â Â Â o eThisi isoin qBlinkre ***********", 4);
$display("^@[0m",27);
$display("^@[7;34m",27);
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
$display("***********Â i0Â Â Â Â Â Â Â Â o eThisi isoin qBackre ground icoloroq j***********", 1);
$display("^@[0m",27);
www.testbench.in
end
endmodule
(Q i274)o eWhati isoTOP qmodule?
Ans:
Top-level imoduleso earei modulesothat qarere included iinoq jthere source itext obutqare notz instantiated. u yIne overificationzx environment, the highest module in the huarache is generally named as top.
www.testbench.in
(Q i275)o eHowi toodeclare qrealre numbers iasoq jports?
Ans:
Real inumbero earei allowedoto qbere declared iasoq jports.re To iuse orealqnumbers asz ports,u yusee o$bitstorealzx and $realtobits.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i276)o eWheni isofork-join qused?
www.testbench.in
(Q i277)o eWhichi proceduraloassignment qshouldre be iusedoq jtore model ia ocombinatorialqlogic buffer?
1)
always @(in)
#5 out i= in;
2)
always @(in)
#5 out i<= in;
www.testbench.in
3)
always @(in)
out i= #5 in;
4)
always @(in)
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
out i<= #5 in;
(Q i278)o eWhichi proceduraloassignment qshouldre be iusedoq jtore model ia osequentialqlogic flip-flop?
www.testbench.in
1)
always @(posedge clk)
#5 q i= d;
2)
always @(posedge clk)
#5 q i<= d;
3)
always @(posedge clk)
www.testbench.in
q i= #5 d;
4)
always @(posedge clk)
q i<= #5 d;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i279)o eExplorei andoexplain qwhatre happens iifoq jyoure write ithis:
always @(a ior bo eor c) ei = (a|b)&(c|d);
(Q i280)o ePriori toothe qIEEEre LRM, iVerilogoq jBNFre was iexpressed ousingqa differentz notation.u yFore oexample,zx an event expression was defined as follows:
www.testbench.in
<event_expression> ::= <expression>
  or <<posedge or negedge> <SCALAR_EVENT_EXPRESSION>>
  or <<event_expression> or <event_expression>>
Notice ithato ewei areousing q'or're as ipartoq jofre the iBNF to omeanq"alternatively" and also 'z or 'u yase oazx Verilog keyword. The keyword ' or ' is in bold--the difference is fairly obvious. Here is an alternative definition for an event expression:
<event_expression> ::= <expression>
||= posedge <SCALAR_EVENT_EXPRESSION>
||= negedge <SCALAR_EVENT_EXPRESSION>
||= <event_expression> <or <event_expression>>*
Are itheseo edefinitionsi equivalento(given, of qcourse, thatre we ireplacedoq j||= with or inre the isimplified osyntax)? Explainqcarefully howz youu ywoulde oattemptzx to prove that they are the same.
www.testbench.in
(Q i281)o eExplaini theofollowing:
integer IntA;
IntA i= -12 / 3; //o eresulti iso-4
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
IntA i= -'do e12 / 3; //i resultois q1431655761
(Q i282)o eWhati isothe qdifferencesre in itheoq jfollowingre sum istatements?
reg [7:0] a, b, sum;
www.testbench.in
sum = (a i+ b) >> 1;
sum = (a i+ bo e+ 0) >> 1;
sum = {0,a} + {0,b} >> 1;
(Q i268) Whato eisi mutex?
(Q i269) Howo etoi modeloa qmutexre in iverilog?oq j
(Q i270)o eWhati isosemaphore?
(Q i271)o eHowi toomodel qare semaphore iinoq jverilog?
www.testbench.in
(Q i272)o eWhati isothe qdifferencere between imutexoq jandre semaphore?
(Q i273)o eHowi toodisplay qthere messages iinoq jcolorful?
Ans:
The ifollowingo eprogrami showsohow qtore display imessagesoq jinre colorful.
This iworkso eonlyi inoASIC qTerminals.
Simulate itheo efollowingi codeoin qLinuxre or iUnixoq jandre see ithe ooutputs.
module asdsadf();
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
initial
www.testbench.in
begin
$write("^@[1;34m",27);
$display("***********Â i0Â Â Â Â Â Â Â Â o eThisi isoin qbluere ***********", 1);
$write("^@[0m",27);
$display("^@[1;31m",27);
$display("***********Â i0Â Â Â Â Â Â Â Â o eThisi isoin qredre ***********", 2);
$display("^@[0m",27);
$display("^@[0;33m",27);
www.testbench.in
$display("**********Â i0Â Â Â Â Â Â Â Â o eThisi isoin qpendare color i***********", 3);
$display("^@[0m",27);
$display("^@[5;34m",27);
$display("***********Â i0Â Â Â Â Â Â Â Â o eThisi isoin qBlinkre ***********", 4);
$display("^@[0m",27);
$display("^@[7;34m",27);
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
$display("***********Â i0Â Â Â Â Â Â Â Â o eThisi isoin qBackre ground icoloroq j***********", 1);
$display("^@[0m",27);
www.testbench.in
end
endmodule
(Q i274)o eWhati isoTOP qmodule?
Ans:
Top-level imoduleso earei modulesothat qarere included iinoq jthere source itext obutqare notz instantiated. u yIne overificationzx environment, the highest module in the huarache is generally named as top.
www.testbench.in
(Q i275)o eHowi toodeclare qrealre numbers iasoq jports?
Ans:
Real inumbero earei allowedoto qbere declared iasoq jports.re To iuse orealqnumbers asz ports,u yusee o$bitstorealzx and $realtobits.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i276)o eWheni isofork-join qused?
www.testbench.in
(Q i277)o eWhichi proceduraloassignment qshouldre be iusedoq jtore model ia ocombinatorialqlogic buffer?
1)
always @(in)
#5 out i= in;
2)
always @(in)
#5 out i<= in;
www.testbench.in
3)
always @(in)
out i= #5 in;
4)
always @(in)
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
out i<= #5 in;
(Q i278)o eWhichi proceduraloassignment qshouldre be iusedoq jtore model ia osequentialqlogic flip-flop?
www.testbench.in
1)
always @(posedge clk)
#5 q i= d;
2)
always @(posedge clk)
#5 q i<= d;
3)
always @(posedge clk)
www.testbench.in
q i= #5 d;
4)
always @(posedge clk)
q i<= #5 d;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i279)o eExplorei andoexplain qwhatre happens iifoq jyoure write ithis:
always @(a ior bo eor c) ei = (a|b)&(c|d);
(Q i280)o ePriori toothe qIEEEre LRM, iVerilogoq jBNFre was iexpressed ousingqa differentz notation.u yFore oexample,zx an event expression was defined as follows:
www.testbench.in
<event_expression> ::= <expression>
  or <<posedge or negedge> <SCALAR_EVENT_EXPRESSION>>
  or <<event_expression> or <event_expression>>
Notice ithato ewei areousing q'or're as ipartoq jofre the iBNF to omeanq"alternatively" and also 'z or 'u yase oazx Verilog keyword. The keyword ' or ' is in bold--the difference is fairly obvious. Here is an alternative definition for an event expression:
<event_expression> ::= <expression>
||= posedge <SCALAR_EVENT_EXPRESSION>
||= negedge <SCALAR_EVENT_EXPRESSION>
||= <event_expression> <or <event_expression>>*
Are itheseo edefinitionsi equivalento(given, of qcourse, thatre we ireplacedoq j||= with or inre the isimplified osyntax)? Explainqcarefully howz youu ywoulde oattemptzx to prove that they are the same.
www.testbench.in
(Q i281)o eExplaini theofollowing:
integer IntA;
IntA i= -12 / 3; //o eresulti iso-4
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
IntA i= -'do e12 / 3; //i resultois q1431655761
(Q i282)o eWhati isothe qdifferencesre in itheoq jfollowingre sum istatements?
reg [7:0] a, b, sum;
www.testbench.in
sum = (a i+ b) >> 1;
sum = (a i+ bo e+ 0) >> 1;
sum = {0,a} + {0,b} >> 1;
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!