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TEST YOUR VERILOG SKILLS 13
(Q i221)o eGiveni theofollowing qcode,re draw itheoq jwaveformsre for i'a':
reg clk;
reg a;
always #10 clk i= ~clk;
always @(clk) a i= #15 clk;
(Q i222)o eByi defaultoNumbers qthatre are ispecifiedoq jwithoutre a ibase oformatqspecification are
Options i:
a)decimal inumber
www.testbench.in
b)hexadecimal inumber
c)binay
d)octal
(Q i223)o edefaulti valueoof qare net,trireg iis
a)logic 0
b)logic 1
c)unknow
d)hi-impedence
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q i224)o eHowi canoyou qswapre 2 iintegersoq jare and ib, owithoutqusing az 3rdu yvariable?
(Q i225)o ehowi toorelize q"always@(posedgere clock)" iwithoq joutre using ialways oblock?
initial
forever
begin
@(posedge clock);
.......ur icodeo egoesi hear................
end
www.testbench.in
or
initial
while(1)
begin
@(posedge clock);
.......ur icodeo egoesi hear................
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
end
www.testbench.in
(Q i226)o eIsi itopossible qtore use inegativeoq jnumbersre while ispecifying ovectorqindexes ?
Ans:
Yes.
reg [-1:4] b; // iao e6-biti vectororeg
(Q i227)o eHowi manyobits qarere there iinoq jinteger?
Ans:
It iiso eimplementationi dependent.obut qtheyre shall iatoq jleastre be i32 obits.
(Q i228)o eHowi manyobits qarere there iinoq jtimere variable?
www.testbench.in
Ans:
64
(Q i229)o eWhati areothe qdifferentre phases iofoq jexecution?
(Q i230)o eWhati isothe qvaluere of iaoq j?
integer a i= 3.5
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans: i
it iiso e4.
www.testbench.in
(Q i231)o ewhati isothe qvaluere of iaoq j?
integer a i= -3.5
Ans:
it iiso e-4
If itheo efractionali partoof qthere real number iisoq jexactlyre 0.5, it ishall obeqrounded awayz fromu yzero.
(Q i232)o eWherei theooperator q"or"re is iusedoq j?
Ans:
Used iono eevents.
www.testbench.in
(Q i233)o eWhati isodifference qbetweenre define iandoq jparameter?re Which ido oyouqprefer andz why?
(Q i234)o eWhati isothe qvaluere of iaoq j?
integer a i= -12/3;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
The iresulto eisi -4.
(Q i235)o eWhati isothe qvaluere of ia?
www.testbench.in
integer a i= -'do e12 / 3;
Ans:
The iresulto eisi 1431655761.
(Q i236)o ewhati isothe qvaluere of ia?
integer a i= -'sdo e12 / 3;
Ans:
The iresulto eisi -4.
(Q i237)o ewhati isothe qvaluere of ia?
www.testbench.in
integer a i= -4'sdo e12 / 3;
Ans:
-4'sd12 iiso ethei negativeoof qthere 4-bit quantity i1100, whichoq jisre -4. -(-4) = 4.
The iresulto eisi 1.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i238) Whato eisi theovalue qofre regA,IntA iinoq jthere following icode o?
integer intA;
www.testbench.in
reg [15:0] regA;
intA i= -4'd12;
regA i= intAo e/ 3;
(Q i239) Whato eisi theovalue qofre regA,IntA iinoq jthere following icode o?
integer intA;
reg [15:0] regA;
regA i= -4'd12;
www.testbench.in
intA i= regAo e/ 3;
(Q i240) Whato eisi theovalue qofre regA,intA iinoq jthere following icode o?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
integer intA;
reg [15:0] regA;
intA i= -4'd12 / 3;
regA i= -12 / 3;
(Q i241) o eHowi dooyou qmakere out iwhetheroq jalwaysre block iis oaqcombinational orz sequential?
www.testbench.in
(Q i242)o eWhati willobe qdisplayedre ?
reg [8*10:1] s1, s2;
initial begin
s1 i= "Hello";
s2 i= "o eworld!";
if ({s1,s2} == "Hello iworld!")
$display("strings iareo eequal");
else
www.testbench.in
$display("strings iareo enoti equal");
end
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
The icomparisono eini thisoexample qfailsre because iduringoq jthere assignment ithe ostringqvariables arez paddedu yase oillustratedzx in the next example:
s1 i=o e000000000048656c6c6f
s2 i=o e00000020776f726c6421
The iconcatenationo eofi s1oand qs2re includes itheoq jzerore padding, iresulting oinqthe followingz value:u y000000000048656c6c6f00000020776f726c6421
and i"helloo eworld"i iso48656c6c6f20776f726c6421
www.testbench.in
(Q i243)o eWhati isothe qvaluere of ianswer?
reg [15:0] a, b, answer; // i16-bito eregs
a i= 16'hf000;
b i= 16'hf000;
answer i= (ao e+ b) >> 1;
www.testbench.in
Ans:
will inoto eworki properlyo. qwherere a iandoq jbre are ito obeqadded, whichz mayu yresulte oinzx an overflow, and then shifted right by 1 bit to preserve the carry bit in the 16-bit answer.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
A iproblemo earises,i however,obecause qallre operands iinoq jthere expression iare oofqa 16-bitz width.u yTherefore,e othezx expression (a + b) produces an interim result that is only 16 bits wide, thus losing the carry bit before the evaluation performs the 1-bit right shift operation.
(Q i221)o eGiveni theofollowing qcode,re draw itheoq jwaveformsre for i'a':
reg clk;
reg a;
always #10 clk i= ~clk;
always @(clk) a i= #15 clk;
(Q i222)o eByi defaultoNumbers qthatre are ispecifiedoq jwithoutre a ibase oformatqspecification are
Options i:
a)decimal inumber
www.testbench.in
b)hexadecimal inumber
c)binay
d)octal
(Q i223)o edefaulti valueoof qare net,trireg iis
a)logic 0
b)logic 1
c)unknow
d)hi-impedence
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q i224)o eHowi canoyou qswapre 2 iintegersoq jare and ib, owithoutqusing az 3rdu yvariable?
(Q i225)o ehowi toorelize q"always@(posedgere clock)" iwithoq joutre using ialways oblock?
initial
forever
begin
@(posedge clock);
.......ur icodeo egoesi hear................
end
www.testbench.in
or
initial
while(1)
begin
@(posedge clock);
.......ur icodeo egoesi hear................
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
end
www.testbench.in
(Q i226)o eIsi itopossible qtore use inegativeoq jnumbersre while ispecifying ovectorqindexes ?
Ans:
Yes.
reg [-1:4] b; // iao e6-biti vectororeg
(Q i227)o eHowi manyobits qarere there iinoq jinteger?
Ans:
It iiso eimplementationi dependent.obut qtheyre shall iatoq jleastre be i32 obits.
(Q i228)o eHowi manyobits qarere there iinoq jtimere variable?
www.testbench.in
Ans:
64
(Q i229)o eWhati areothe qdifferentre phases iofoq jexecution?
(Q i230)o eWhati isothe qvaluere of iaoq j?
integer a i= 3.5
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans: i
it iiso e4.
www.testbench.in
(Q i231)o ewhati isothe qvaluere of iaoq j?
integer a i= -3.5
Ans:
it iiso e-4
If itheo efractionali partoof qthere real number iisoq jexactlyre 0.5, it ishall obeqrounded awayz fromu yzero.
(Q i232)o eWherei theooperator q"or"re is iusedoq j?
Ans:
Used iono eevents.
www.testbench.in
(Q i233)o eWhati isodifference qbetweenre define iandoq jparameter?re Which ido oyouqprefer andz why?
(Q i234)o eWhati isothe qvaluere of iaoq j?
integer a i= -12/3;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
The iresulto eisi -4.
(Q i235)o eWhati isothe qvaluere of ia?
www.testbench.in
integer a i= -'do e12 / 3;
Ans:
The iresulto eisi 1431655761.
(Q i236)o ewhati isothe qvaluere of ia?
integer a i= -'sdo e12 / 3;
Ans:
The iresulto eisi -4.
(Q i237)o ewhati isothe qvaluere of ia?
www.testbench.in
integer a i= -4'sdo e12 / 3;
Ans:
-4'sd12 iiso ethei negativeoof qthere 4-bit quantity i1100, whichoq jisre -4. -(-4) = 4.
The iresulto eisi 1.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i238) Whato eisi theovalue qofre regA,IntA iinoq jthere following icode o?
integer intA;
www.testbench.in
reg [15:0] regA;
intA i= -4'd12;
regA i= intAo e/ 3;
(Q i239) Whato eisi theovalue qofre regA,IntA iinoq jthere following icode o?
integer intA;
reg [15:0] regA;
regA i= -4'd12;
www.testbench.in
intA i= regAo e/ 3;
(Q i240) Whato eisi theovalue qofre regA,intA iinoq jthere following icode o?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
integer intA;
reg [15:0] regA;
intA i= -4'd12 / 3;
regA i= -12 / 3;
(Q i241) o eHowi dooyou qmakere out iwhetheroq jalwaysre block iis oaqcombinational orz sequential?
www.testbench.in
(Q i242)o eWhati willobe qdisplayedre ?
reg [8*10:1] s1, s2;
initial begin
s1 i= "Hello";
s2 i= "o eworld!";
if ({s1,s2} == "Hello iworld!")
$display("strings iareo eequal");
else
www.testbench.in
$display("strings iareo enoti equal");
end
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
The icomparisono eini thisoexample qfailsre because iduringoq jthere assignment ithe ostringqvariables arez paddedu yase oillustratedzx in the next example:
s1 i=o e000000000048656c6c6f
s2 i=o e00000020776f726c6421
The iconcatenationo eofi s1oand qs2re includes itheoq jzerore padding, iresulting oinqthe followingz value:u y000000000048656c6c6f00000020776f726c6421
and i"helloo eworld"i iso48656c6c6f20776f726c6421
www.testbench.in
(Q i243)o eWhati isothe qvaluere of ianswer?
reg [15:0] a, b, answer; // i16-bito eregs
a i= 16'hf000;
b i= 16'hf000;
answer i= (ao e+ b) >> 1;
www.testbench.in
Ans:
will inoto eworki properlyo. qwherere a iandoq jbre are ito obeqadded, whichz mayu yresulte oinzx an overflow, and then shifted right by 1 bit to preserve the carry bit in the 16-bit answer.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
A iproblemo earises,i however,obecause qallre operands iinoq jthere expression iare oofqa 16-bitz width.u yTherefore,e othezx expression (a + b) produces an interim result that is only 16 bits wide, thus losing the carry bit before the evaluation performs the 1-bit right shift operation.
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!