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Specman E
Interview Questions
TEST YOUR VERILOG SKILLS 13
(Q
i
221)
o
e
Given
i
the
o
following
q
code,
r
e
draw
i
the
o
q
j
waveforms
r
e
for
i
'a':
reg
i
clk;
reg
i
a;
always
i
#10
o
e
clk
i
=
o
~clk;
always
i
@(clk)
o
e
a
i
=
o
#15
q
clk;
(Q
i
222)
o
e
By
i
default
o
Numbers
q
that
r
e
are
i
specified
o
q
j
without
r
e
a
i
base
o
format
q
specification are
Options
i
:
a)decimal
i
number
www.testbench.in
b)hexadecimal
i
number
c)binay
d)octal
(Q
i
223)
o
e
default
i
value
o
of
q
a
r
e
net,trireg
i
is
a)logic
i
0
b)logic
i
1
c)unknow
d)hi-impedence
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q
i
224)
o
e
How
i
can
o
you
q
swap
r
e
2
i
integers
o
q
j
a
r
e
and
i
b,
o
without
q
using a
z
3rd
u
y
variable?
(Q
i
225)
o
e
how
i
to
o
relize
q
"
always
@(
posedge
r
e
clock
)
"
i
with
o
q
j
out
r
e
using
i
always
o
block?
initial
forever
begin
@(posedge
i
clock);
.......ur
i
code
o
e
goes
i
hear................
end
www.testbench.in
or
initial
while(1)
begin
@(posedge
i
clock);
.......ur
i
code
o
e
goes
i
hear................
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
end
www.testbench.in
(Q
i
226)
o
e
Is
i
it
o
possible
q
to
r
e
use
i
negative
o
q
j
numbers
r
e
while
i
specifying
o
vector
q
indexes ?
Ans:
Yes.
reg
i
[-1:4]
o
e
b;
i
//
o
a
q
6-bit
r
e
vector
i
reg
(Q
i
227)
o
e
How
i
many
o
bits
q
are
r
e
there
i
in
o
q
j
integer?
Ans:
It
i
is
o
e
implementation
i
dependent.
o
but
q
they
r
e
shall
i
at
o
q
j
least
r
e
be
i
32
o
bits.
(Q
i
228)
o
e
How
i
many
o
bits
q
are
r
e
there
i
in
o
q
j
time
r
e
variable?
www.testbench.in
Ans:
64
(Q
i
229)
o
e
What
i
are
o
the
q
different
r
e
phases
i
of
o
q
j
execution?
(Q
i
230)
o
e
What
i
is
o
the
q
value
r
e
of
i
a
o
q
j
?
integer
i
a
o
e
=
i
3.5
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
i
it
i
is
o
e
4.
www.testbench.in
(Q
i
231)
o
e
what
i
is
o
the
q
value
r
e
of
i
a
o
q
j
?
integer
i
a
o
e
=
i
-3.5
o
Ans:
it
i
is
o
e
-4
If
i
the
o
e
fractional
i
part
o
of
q
the
r
e
real
i
number
o
q
j
is
r
e
exactly
i
0.5,
o
it
q
shall be
z
rounded
u
y
away
e
o
from
z
x
zero.
(Q
i
232)
o
e
Where
i
the
o
operator
q
"
or
"
r
e
is
i
used
o
q
j
?
Ans:
Used
i
on
o
e
events.
www.testbench.in
(Q
i
233)
o
e
What
i
is
o
difference
q
between
r
e
define
i
and
o
q
j
parameter?
r
e
Which
i
do
o
you
q
prefer and
z
why?
(Q
i
234)
o
e
What
i
is
o
the
q
value
r
e
of
i
a
o
q
j
?
integer
i
a
o
e
=
i
-12/3;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
The
i
result
o
e
is
i
-4.
(Q
i
235)
o
e
What
i
is
o
the
q
value
r
e
of
i
a?
www.testbench.in
integer
i
a
o
e
=
i
-'d
o
12
q
/
r
e
3;
Ans:
The
i
result
o
e
is
i
1431655761.
(Q
i
236)
o
e
what
i
is
o
the
q
value
r
e
of
i
a?
integer
i
a
o
e
=
i
o
-'sd
q
12
r
e
/
i
3;
o
q
j
Ans:
The
i
result
o
e
is
i
-4.
(Q
i
237)
o
e
what
i
is
o
the
q
value
r
e
of
i
a?
www.testbench.in
integer
i
a
o
e
=
i
o
-4'sd
q
12
r
e
/
i
3;
o
q
j
Ans:
i
-4'sd12
o
e
is
i
the
o
negative
q
of
r
e
the
i
4-bit
o
q
j
quantity
r
e
1100,
i
which
o
is
q
-4. -(-4)
z
=
u
y
4.
The
i
result
o
e
is
i
1.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
238)
o
e
i
What
o
is
q
the
r
e
value
i
of
o
q
j
regA,IntA
r
e
in
i
the
o
following
q
code ?
integer
i
intA;
www.testbench.in
reg
i
[15:0]
o
e
regA;
intA
i
=
o
e
-4'd12;
regA
i
=
o
e
intA
i
/
o
3;
q
(Q
i
239)
o
e
i
What
o
is
q
the
r
e
value
i
of
o
q
j
regA,IntA
r
e
in
i
the
o
following
q
code ?
integer
i
intA;
reg
i
[15:0]
o
e
regA;
regA
i
=
o
e
-4'd12;
i
www.testbench.in
intA
i
=
o
e
regA
i
/
o
3;
q
(Q
i
240)
o
e
i
What
o
is
q
the
r
e
value
i
of
o
q
j
regA,intA
r
e
in
i
the
o
following
q
code ?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
integer
i
intA;
reg
i
[15:0]
o
e
regA;
intA
i
=
o
e
-4'd12
i
/
o
3;
regA
i
=
o
e
-12
i
/
o
3;
(Q
i
241)
o
e
i
o
q
r
e
i
o
q
j
r
e
i
How
o
do
q
you make
z
out
u
y
whether
e
o
always
z
x
block is a combinational or sequential?
www.testbench.in
(Q
i
242)
o
e
What
i
will
o
be
q
displayed
r
e
?
reg
i
[8*10:1]
o
e
s1,
i
s2;
initial
i
begin
s1
i
=
o
e
"
Hello
";
s2
i
=
o
e
"
i
world
!
";
if
i
({s1,s2}
o
e
==
i
"
Hello
o
world
!
")
$display("
strings
i
are
o
e
equal
");
else
www.testbench.in
$display("
strings
i
are
o
e
not
i
equal
");
end
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
The
i
comparison
o
e
in
i
this
o
example
q
fails
r
e
because
i
during
o
q
j
the
r
e
assignment
i
the
o
string
q
variables are
z
padded
u
y
as
e
o
illustrated
z
x
in the next example:
s1
i
=
o
e
000000000048656c6c6f
s2
i
=
o
e
00000020776f726c6421
The
i
concatenation
o
e
of
i
s1
o
and
q
s2
r
e
includes
i
the
o
q
j
zero
r
e
padding,
i
resulting
o
in
q
the following
z
value:
u
y
000000000048656c6c6f00000020776f726c6421
and
i
"
hello
o
e
world
"
i
is
o
48656c6c6f20776f726c6421
www.testbench.in
(Q
i
243)
o
e
What
i
is
o
the
q
value
r
e
of
i
answer?
reg
i
[15:0]
o
e
a,
i
b,
o
answer;
q
//
r
e
16-bit
i
regs
a
i
=
o
e
16'hf000;
b
i
=
o
e
16'hf000;
answer
i
=
o
e
(a
i
+
o
b)
q
>>
r
e
1;
i
www.testbench.in
Ans:
will
i
not
o
e
work
i
properly
o
.
q
where
r
e
a
i
and
o
q
j
b
r
e
are
i
to
o
be
q
added, which
z
may
u
y
result
e
o
in
z
x
an overflow, and then shifted right by 1 bit to preserve the carry bit in the 16-bit answer.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
A
i
problem
o
e
arises,
i
however,
o
because
q
all
r
e
operands
i
in
o
q
j
the
r
e
expression
i
are
o
of
q
a 16-bit
z
width.
u
y
Therefore,
e
o
the
z
x
expression (a + b) produces an interim result that is only 16 bits wide, thus losing the carry bit before the evaluation performs the 1-bit right shift operation.
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
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