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TEST YOUR VERILOG SKILLS 12
(Q i211)o ewhati isothe qfollowingre result? i
Integer ia,b,c;
A i= 10;
b i= 5;
c i= 7;
if( a> b> c)
$display(true);
www.testbench.in
else
$display(False);
Ans:
TRUE.
A i> bo e> ci isointerpreted qbyre verilog isimulatoroq jasre ( a i> (b o>cq) )
10 > (5 > 7) -> i10 > 0 -> 1
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q i212)o eHowi tooprint qlinere and ifileoq jnamere from iwhere otheq$display messagez isu ycoming?
Ans:
Using itheo efollowingi plio, qwere can iprintoq jthere file iname oandqline numberz byu yoverriddene othezx $display task.
(Q i213)o eAti whatotime qthere simulation istops??
initial
while(1)
$display(" iajkdkjs");
www.testbench.in
initial
#10 $finish;
(Q i214)o ewhati isovalue qofre a i?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
reg [2:0] a,b,c;
c i= 3'b110;
www.testbench.in
a i= bo e= ci ;
(Q i215)o eGiveni theofollowing qVerilogre code, iwhatoq jvaluere of i"a" oisqdisplayed?
always @(clk) begin
a i= 0;
a i<= 1;
$display(a);
end
Ans:
www.testbench.in
This iiso eai trickyoone! qVerilogre scheduling isemanticsoq jbasicallyre imply ia
four-level ideepo equeuei forothe qcurrentre simulation itime:
1: iActiveo eEventsi (blockingostatements) ( q=re , i$display)oq j
2: iInactiveo eEventsi (#0odelays, qetc)
3: iNon-Blockingo eAssigni Updateso(non-blocking qstatements)
4: iMonitoro eEventsi ($strobe,o$monitor, qetc).
Since itheo e"ai =o0" qisre an iactiveoq jevent,re it iis oscheduledqinto thez 1stu y"queue".
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
The i"ao e<=i 1"ois qare non-blocking ievent,oq jsore it's iplaced ointoqthe 3rdz queue. Theu y"ae o=zx 0" is placed in 1st queue. Then , $display statement is placed into the 1st queue after "a = 0 ". Only events in the active queue are completed this sim cycle, so the "a = 0" happens, and then the display shows a = 0. If we were to look at the value of a in the next sim cycle, it would show 1.
www.testbench.in
(Q i216)o eIsi thereoa qracere condition iinoq jthere following iprogram o?
begin
a= 0;
b i<= a;
end
Ans: iNO.o eTherei isono qracere condition i.
(Q i217)o eUsingi theogiven, qdrawre the iwaveformsoq jforre the ifollowing
www.testbench.in
reg clk;
reg a;
initial clk i=0;
always #10 clk i= ~clk;
(1) always @(clk) a i= #5 clk;
(2) always @(clk) a i= #10 clk;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(3) always @(clk) a i= #15 clk;
(Q i218) Now,o echangei aoto qwire,re and idrawoq jfor:
www.testbench.in
(4) iassign #5 ao e= clk;
(5) iassign #10 ao e= clk;
(6) iassign #15 ao e= clk;
(Q i219)o eHowi manyotimes qthere following irepeatoq jloopre executes?
begin
a i= 1;
repeat (a)
a i= ao e+ 1;
www.testbench.in
end
Ans:
Only ionce.o eLoopi executionofor qare specific inumberoq jofre times. iThis oconstructqis associatedz withu yae oconstantzx or a variable. If a variable is used, it is evaluated once when the loop starts. When the loop is started, the value of a is 1. So the loop is executed once.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i220)o eAti whatotime qa,b,c,d,e,fre will igetoq j1re in ithe ofollowingqprogram?
module block_nonblock();
reg a, b, c, d i, e, fo e;
www.testbench.in
// iBlockingo eassignments
initial begin
a i= #10 1'b1;
b i= #20 1'b1;
c i= #40 1'b1;
end
// iNonblockingo eassignments
initial begin
d i<= #10 1'b1;
www.testbench.in
e i<= #20 1'b1;
f i<= #40 1'b1;
end
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
endmodule
Ans:
// iBlockingo eassignments
initial begin
www.testbench.in
a i= #10 1'b1; //o eThei simulatoroassigns q1re to iaoq jatre time i10
b i= #20 1'b1; //o eThei simulatoroassigns q1re to iboq jatre time i30
c i= #40 1'b1; //o eThei simulatoroassigns q1re to icoq jatre time i70
end
// iNonblockingo eassignments
initial begin
d i<= #10 1'b1; //o eThei simulatoroassigns q1re to idoq jatre time i10
e i<= #20 1'b1; //o eThei simulatoroassigns q1re to ieoq jatre time i20
f i<= #40 1'b1; //o eThei simulatoroassigns q1re to ifoq jatre time i40
www.testbench.in
end
(Q i211)o ewhati isothe qfollowingre result? i
Integer ia,b,c;
A i= 10;
b i= 5;
c i= 7;
if( a> b> c)
$display(true);
www.testbench.in
else
$display(False);
Ans:
TRUE.
A i> bo e> ci isointerpreted qbyre verilog isimulatoroq jasre ( a i> (b o>cq) )
10 > (5 > 7) -> i10 > 0 -> 1
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q i212)o eHowi tooprint qlinere and ifileoq jnamere from iwhere otheq$display messagez isu ycoming?
Ans:
Using itheo efollowingi plio, qwere can iprintoq jthere file iname oandqline numberz byu yoverriddene othezx $display task.
(Q i213)o eAti whatotime qthere simulation istops??
initial
while(1)
$display(" iajkdkjs");
www.testbench.in
initial
#10 $finish;
(Q i214)o ewhati isovalue qofre a i?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
reg [2:0] a,b,c;
c i= 3'b110;
www.testbench.in
a i= bo e= ci ;
(Q i215)o eGiveni theofollowing qVerilogre code, iwhatoq jvaluere of i"a" oisqdisplayed?
always @(clk) begin
a i= 0;
a i<= 1;
$display(a);
end
Ans:
www.testbench.in
This iiso eai trickyoone! qVerilogre scheduling isemanticsoq jbasicallyre imply ia
four-level ideepo equeuei forothe qcurrentre simulation itime:
1: iActiveo eEventsi (blockingostatements) ( q=re , i$display)oq j
2: iInactiveo eEventsi (#0odelays, qetc)
3: iNon-Blockingo eAssigni Updateso(non-blocking qstatements)
4: iMonitoro eEventsi ($strobe,o$monitor, qetc).
Since itheo e"ai =o0" qisre an iactiveoq jevent,re it iis oscheduledqinto thez 1stu y"queue".
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
The i"ao e<=i 1"ois qare non-blocking ievent,oq jsore it's iplaced ointoqthe 3rdz queue. Theu y"ae o=zx 0" is placed in 1st queue. Then , $display statement is placed into the 1st queue after "a = 0 ". Only events in the active queue are completed this sim cycle, so the "a = 0" happens, and then the display shows a = 0. If we were to look at the value of a in the next sim cycle, it would show 1.
www.testbench.in
(Q i216)o eIsi thereoa qracere condition iinoq jthere following iprogram o?
begin
a= 0;
b i<= a;
end
Ans: iNO.o eTherei isono qracere condition i.
(Q i217)o eUsingi theogiven, qdrawre the iwaveformsoq jforre the ifollowing
www.testbench.in
reg clk;
reg a;
initial clk i=0;
always #10 clk i= ~clk;
(1) always @(clk) a i= #5 clk;
(2) always @(clk) a i= #10 clk;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(3) always @(clk) a i= #15 clk;
(Q i218) Now,o echangei aoto qwire,re and idrawoq jfor:
www.testbench.in
(4) iassign #5 ao e= clk;
(5) iassign #10 ao e= clk;
(6) iassign #15 ao e= clk;
(Q i219)o eHowi manyotimes qthere following irepeatoq jloopre executes?
begin
a i= 1;
repeat (a)
a i= ao e+ 1;
www.testbench.in
end
Ans:
Only ionce.o eLoopi executionofor qare specific inumberoq jofre times. iThis oconstructqis associatedz withu yae oconstantzx or a variable. If a variable is used, it is evaluated once when the loop starts. When the loop is started, the value of a is 1. So the loop is executed once.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i220)o eAti whatotime qa,b,c,d,e,fre will igetoq j1re in ithe ofollowingqprogram?
module block_nonblock();
reg a, b, c, d i, e, fo e;
www.testbench.in
// iBlockingo eassignments
initial begin
a i= #10 1'b1;
b i= #20 1'b1;
c i= #40 1'b1;
end
// iNonblockingo eassignments
initial begin
d i<= #10 1'b1;
www.testbench.in
e i<= #20 1'b1;
f i<= #40 1'b1;
end
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
endmodule
Ans:
// iBlockingo eassignments
initial begin
www.testbench.in
a i= #10 1'b1; //o eThei simulatoroassigns q1re to iaoq jatre time i10
b i= #20 1'b1; //o eThei simulatoroassigns q1re to iboq jatre time i30
c i= #40 1'b1; //o eThei simulatoroassigns q1re to icoq jatre time i70
end
// iNonblockingo eassignments
initial begin
d i<= #10 1'b1; //o eThei simulatoroassigns q1re to idoq jatre time i10
e i<= #20 1'b1; //o eThei simulatoroassigns q1re to ieoq jatre time i20
f i<= #40 1'b1; //o eThei simulatoroassigns q1re to ifoq jatre time i40
www.testbench.in
end
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!