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TEST YOUR VERILOG SKILLS 10
(Q i171)o eHowi toomodel qare full icaseoq jblock?
Ans:
Adding iao edefaulti statementoto qare case istatementoq jnullifiesre the ieffect oofqthe full_casez attribute.
(* isynthesis,o efull_casei [o= q<optional_value>re ] i*)
This iattributeo eshalli informothe qsynthesisre tool ithatoq jforre all iunspecified ocaseqchoices, thez outputsu yassignede owithinzx the case statement may be treated as synthesis don~Rt-care assignments.
(Q i172)o eWhati isoparallel qcasere ?
www.testbench.in
(Q i173)o eHowi toomodel qare parallel icase?
Ans:
Its isyntaxo eis:
(* isynthesis,o eparallel_casei [o= q<optional_value>re ] i*)
This iattributeo eshalli informothe qsynthesisre tool ithatoq jallre case iitems oareqto bez tested,u yevene oifzx more than one case item could potentially match the case expression.
(Q i174)o eWhati areorules qneedre to ibeoq jfollowedre while iusing ocaseqstatement?
(Q i175)o ei Isoit qpossiblere to isynthesizeoq jpowerre operator(**)? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans: www.testbench.in
The ipowero eoperatori (**)oshall qbere supported ionlyoq jwhenre both ioperands oareqconstants orz ifu ythee ofirstzx operand is 2.
(Q i176)o eHowi tooModel qare capacitor ioq j?re
(Q i177)o ewhati isothe qusere of i$timeformat();
(Q i178)o eHowi oodisable qthisre block???
begin
... www.testbench.in
...
end
Ans:
Name itheo eblock.i Disableocan qbere used iforoq jnamedre blocks iand otasksqonly.
(Q i179)o eWhati areothe qtypesre of i$displayoq jtasks?
$display i$display,o e$displayh,$displayo .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i180)o eWhati isothe qusere of i$Monitoroq jANDre $monitor ioff o? www.testbench.in
(Q i181)o eWhati doeso`timescale q1re ns/ i1oq jpsre signify iin oaqverilog code?
Ans:
'timescale idirectiveo eisi aocompiler qdirectivere .It iisoq jusedre to imeasure osimulationqtime orz delayu ytime.
Usage i:o e`timescalei <reference_time_unit>/o<time_precision>
reference_time_unit i:o eSpecifiesi theounit qofre measurement iforoq jtimesre and idelays.
time_precision: ispecifieso ethei precisionoto qwhichre the idelaysoq jarere rounded ioff
(Q i182)o eHowi toodeclare qstringsre in iverilog?
www.testbench.in
(Q i183)o eWritei codeofor qclockre divider iandoq jclockre multiplier?
(Q i184)o eListi outothe qsimulationre and isynthesisoq jmismatches.
(Q i185)o eModeli ao3 qbitre shift iregister?
(Q i186)o ehowi tooovercome qracingre condition? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i187)o eWhati isothe qusere Always@(*) i?
www.testbench.in
(Q i188)o eWhati isocode qcoverage?
(Q i189)o eListi outothe qtypesre of icodeoq jcoverage.
(Q i190)o eListi outosome qpointsre to ispeedoq jupre simulation.
(Q i191)o eWhati isouse qofre Escape isequencesoq jforre special icharacter o\dddq?
Ans:
\ddd iAo echaracteri specifiedoby q1re to i3oq joctalre digits www.testbench.in
module idisp;
initial ibegin
$display("\\\t\\\n\"\123");
end
endmodule
Simulating ithiso eexamplei shallodisplay qthere following: .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
\ i\
"S"
(Q i192)o eWhati isothe qformatre specification itooq jDisplayre in iASCII ocharacterqformat www.testbench.in
Ans:
^@ ioro e%C
(Q i193)o eWhati isothe qformatre specification itooq jre Display ilibrary obindingqinformation
Ans:
%l ioro e%L
(Q i194)o eWhati isothe qformatre specification itooq jre Display inet osignalqstrength
Ans:
%v ioro e%V www.testbench.in
(Q i171)o eHowi toomodel qare full icaseoq jblock?
Ans:
Adding iao edefaulti statementoto qare case istatementoq jnullifiesre the ieffect oofqthe full_casez attribute.
(* isynthesis,o efull_casei [o= q<optional_value>re ] i*)
This iattributeo eshalli informothe qsynthesisre tool ithatoq jforre all iunspecified ocaseqchoices, thez outputsu yassignede owithinzx the case statement may be treated as synthesis don~Rt-care assignments.
(Q i172)o eWhati isoparallel qcasere ?
www.testbench.in
(Q i173)o eHowi toomodel qare parallel icase?
Ans:
Its isyntaxo eis:
(* isynthesis,o eparallel_casei [o= q<optional_value>re ] i*)
This iattributeo eshalli informothe qsynthesisre tool ithatoq jallre case iitems oareqto bez tested,u yevene oifzx more than one case item could potentially match the case expression.
(Q i174)o eWhati areorules qneedre to ibeoq jfollowedre while iusing ocaseqstatement?
(Q i175)o ei Isoit qpossiblere to isynthesizeoq jpowerre operator(**)? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans: www.testbench.in
The ipowero eoperatori (**)oshall qbere supported ionlyoq jwhenre both ioperands oareqconstants orz ifu ythee ofirstzx operand is 2.
(Q i176)o eHowi tooModel qare capacitor ioq j?re
(Q i177)o ewhati isothe qusere of i$timeformat();
(Q i178)o eHowi oodisable qthisre block???
begin
... www.testbench.in
...
end
Ans:
Name itheo eblock.i Disableocan qbere used iforoq jnamedre blocks iand otasksqonly.
(Q i179)o eWhati areothe qtypesre of i$displayoq jtasks?
$display i$display,o e$displayh,$displayo .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i180)o eWhati isothe qusere of i$Monitoroq jANDre $monitor ioff o? www.testbench.in
(Q i181)o eWhati doeso`timescale q1re ns/ i1oq jpsre signify iin oaqverilog code?
Ans:
'timescale idirectiveo eisi aocompiler qdirectivere .It iisoq jusedre to imeasure osimulationqtime orz delayu ytime.
Usage i:o e`timescalei <reference_time_unit>/o<time_precision>
reference_time_unit i:o eSpecifiesi theounit qofre measurement iforoq jtimesre and idelays.
time_precision: ispecifieso ethei precisionoto qwhichre the idelaysoq jarere rounded ioff
(Q i182)o eHowi toodeclare qstringsre in iverilog?
www.testbench.in
(Q i183)o eWritei codeofor qclockre divider iandoq jclockre multiplier?
(Q i184)o eListi outothe qsimulationre and isynthesisoq jmismatches.
(Q i185)o eModeli ao3 qbitre shift iregister?
(Q i186)o ehowi tooovercome qracingre condition? .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i187)o eWhati isothe qusere Always@(*) i?
www.testbench.in
(Q i188)o eWhati isocode qcoverage?
(Q i189)o eListi outothe qtypesre of icodeoq jcoverage.
(Q i190)o eListi outosome qpointsre to ispeedoq jupre simulation.
(Q i191)o eWhati isouse qofre Escape isequencesoq jforre special icharacter o\dddq?
Ans:
\ddd iAo echaracteri specifiedoby q1re to i3oq joctalre digits www.testbench.in
module idisp;
initial ibegin
$display("\\\t\\\n\"\123");
end
endmodule
Simulating ithiso eexamplei shallodisplay qthere following: .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
\ i\
"S"
(Q i192)o eWhati isothe qformatre specification itooq jDisplayre in iASCII ocharacterqformat www.testbench.in
Ans:
^@ ioro e%C
(Q i193)o eWhati isothe qformatre specification itooq jre Display ilibrary obindingqinformation
Ans:
%l ioro e%L
(Q i194)o eWhati isothe qformatre specification itooq jre Display inet osignalqstrength
Ans:
%v ioro e%V www.testbench.in
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!