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Specman E
Interview Questions
TEST YOUR VERILOG SKILLS 9
(Q
i
161)
o
e
How
i
to
o
model
q
a
r
e
sequential
i
circuit?
Ans:
Sequential
i
logic
o
e
shall
i
be
o
modeled
q
using
r
e
an
i
always
o
q
j
statement
r
e
that
i
has
o
one
q
or more
z
edge
u
y
events
e
o
in
z
x
the event list.
(Q
i
162)
o
e
What
i
is
o
the
q
use
r
e
of
i
$timeformat
o
q
j
?
Ans:
The
i
$timeformat
o
e
system
i
task
o
performs
q
the
r
e
following
i
two
o
q
j
operations:
It
i
sets
o
e
the
i
time
o
unit
q
for
r
e
all
i
later-entered
o
q
j
delays
r
e
entered
i
interactively.
It
i
sets
o
e
the
i
time
o
unit,
q
precision
r
e
number,
i
suffix
o
q
j
string,
r
e
and
i
minimum
o
field
q
width for
z
all
u
y
%t
e
o
formats
z
x
specified in all modules that follow in the source description until another $timeformat system task is invoked.
www.testbench.in
(Q
i
163)
o
e
What
i
is
o
the
q
significance
r
e
of
i
defparam
o
q
j
in
r
e
verilog?
Ans:
Parameter
i
values
o
e
can
i
be
o
changed
q
in
r
e
any
i
module
o
q
j
instance
r
e
in
i
the
o
design
q
with the
z
keyword
u
y
defparam.
e
o
The
z
x
hierarchical name of the module instance can be used to override parameter values.
(Q
i
164)
o
e
Write
i
program
o
for
q
D-FF
r
e
with
i
synchronous
o
q
j
and
r
e
asynchronous
i
reset.
(Q
i
165)
o
e
Whats
i
the
o
notation
q
to
r
e
see
i
hierarchy
o
q
j
in
r
e
display?
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
%
m
www.testbench.in
(Q
i
166)
o
e
How
i
to
o
describe
q
delays
r
e
for
i
structural
o
q
j
models
r
e
such
i
as
o
ASIC
q
cells?
Ans:
Two
i
types
o
e
of
i
HDL
o
constructs
q
are
r
e
often
i
used
o
q
j
to
r
e
describe
i
delays
o
for
q
structural models
z
such
u
y
as
e
o
ASIC
z
x
cells.
They
i
are
o
e
as
i
follows:
Distributed
i
delays,
o
e
which
i
specify
o
the
q
time
r
e
it
i
takes
o
q
j
events
r
e
to
i
propagate
o
through
q
gates and
z
nets
u
y
inside
e
o
the
z
x
module
Module
i
path
o
e
delays,
i
which
o
describe
q
the
r
e
time
i
it
o
q
j
takes
r
e
an
i
event
o
at
q
a source
z
(input
u
y
port
e
o
or
z
x
inout port) to propagate to a destination (output port or inout port)
(Q
i
167)
o
e
How
i
to
o
model
q
a
r
e
tri
i
state
o
q
j
driver?
Ans:
www.testbench.in
Three-state
i
logic
o
e
shall
i
be
o
modeled
q
when
r
e
a
i
variable
o
q
j
is
r
e
assigned
i
the
o
value
q
z. The
z
assignment
u
y
of
e
o
z
z
x
can be conditional or unconditional. If any driver of a signal contains an assignment to the value z, then all the drivers shall contain such an assignment.
module
i
ztest
o
e
(
test2
,
i
test1
,
o
test3
,
q
ena
);
input
i
[
0
:
1
]
o
e
ena
;
input
i
[
7
:
0
]
o
e
test1
,
i
test3
;
output
i
[
7
:
0
]
o
e
test2
;
wire
i
[
7
:
0
]
o
e
test2
;
assign
i
test2
o
e
=
i
(
ena
o
==
q
2'b01
)
r
e
?
i
test1
o
q
j
:
r
e
8'bz
;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
assign
i
test2
o
e
=
i
(
ena
o
==
q
2'b10
)
r
e
?
i
test3
o
q
j
:
r
e
8'bz
;
//
i
test2
o
e
is
i
three-state
o
when
q
ena
r
e
is
i
2~Rb00
o
q
j
or
r
e
2~Rb11.
www.testbench.in
Endmodule
(Q
i
168)
o
e
How
i
to
o
model
q
a
r
e
ROM?
Ans:
An
i
asynchronous
o
e
ROM
i
shall
o
be
q
modeled
r
e
as
i
combinational
o
q
j
logic
r
e
using
i
one
o
of
q
the following
z
styles:
a)
i
One-dimensional
o
e
array
i
with
o
data
q
in
r
e
case
i
statement
o
q
j
.
b)
i
Two-dimensional
o
e
array
i
with
o
data
q
in
r
e
initial
i
statement
o
q
j
.
c)
i
Two-dimensional
o
e
array
i
with
o
data
q
in
r
e
text
i
file
o
q
j
.
(Q
i
169)
o
e
How
i
to
o
model
q
a
r
e
RAM?
www.testbench.in
Ans:
A
i
RAM
o
e
shall
i
be
o
modeled
q
using
r
e
a
i
Verilog
o
q
j
memory
r
e
(a
i
two-dimensional
o
reg
q
array) that
z
has
u
y
the
e
o
attribute
z
x
ram_block associated with it. A RAM element may either be modeled as an edge-sensitive storage element or as a level-sensitive storage element. A RAM data value may be read synchronously or asynchronously.
//
i
A
o
e
RAM
i
element
o
is
q
an
r
e
edge-sensitive
i
storage
o
q
j
element:
module
i
ram_test
(
output
i
wire
o
e
[
7
:
0
]
i
q
,
input
i
wire
o
e
[
7
:
0
]
i
d
,
input
i
wire
o
e
[
6
:
0
]
i
a
,
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
input
i
wire
o
e
clk
,
i
we
);
(*
i
synthesis
,
o
e
ram_block
i
*)
o
reg
q
[
7
:
0
]
r
e
mem
i
[
127
:
0
];
always
i
@(
posedge
o
e
clk
)
i
if
o
(
we
)
q
mem
[
a
]
r
e
<=
i
d
;
www.testbench.in
assign
i
q
o
e
=
i
mem
[
a
];
endmodule
(Q
i
170)
o
e
What
i
is
o
full
q
case?
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
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