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TEST YOUR VERILOG SKILLS 8
(Q i151)o eWhetheri initialoblock qcanre be isynthesized?
Ans:
YES
According itoo eIEEE
(Q i152)o eHowi tooread qdatare from iaoq jfile?
Ans:
Using i$readmemh and $readmem0. Fileo eio
www.testbench.in
(Q i153)o eIllustratei withoexample qthere declaration iofoq jlocalre variable iinside oaqbegin ...endz block?
Ans:
TO ideclareo eai localovariable qinsidere begin...end iblock,oq jthere block ishould obeqnamed.
begin:name_
integer varib;
....
....
end
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i154)o eifi Aoand qBre are itwooq jclkre pulses iwhich oareqout ofz phaseu yande ohavingzx same frequency, how to find which input clk signal is leading? Write verilog code for this.
www.testbench.in
Ans:
Here iiso ethei simpleosolution qforre this. i
All iito eneedsi isoa qflipre flop. i
if iweo ehavei 2oclks, qclk1re and iclk2oq jgivere clk1 ito oD-inputqof flipz flopu yande ootherzx to CLK input of FF.
if iclk1o eisi leadingothe qoutputre is ihigh.oq j
if iclk2o eisi leadingothe qoutputre is ilow.oq j
(Q i155)o ehowi canowe qwritere decoder ifunctionalityoq jinre only ione ostatementqin verilog?
Ans:
www.testbench.in
module decoder(
// iOutputso e
dout,
// iInputso e
din i
);
input [3:0] din;
output [15:0] dout;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
assign dout i= {dino e== 15, dini == 14, dino== 13, din q== 12,
idino e== 11, dini == 10, dino== 9, din q== 8,
www.testbench.in
idino e== 7, dini == 6, dino== 5, din q== 4,
idino e== 3, dini == 2, dino== 1, din q== 0 };
endmodule // idecodero e
(Q i156) Verilogo ecodei toodetect qifre a i64bitoq jpatternre can ibe oexpressedqusing powerz ofu y2e o
Ans:
module pat_det i( data_in, patDetectedo e);
input [31:0] data_in;
output patDetected;
www.testbench.in
wire [4:0] patSum i= data_in[0] + data_in[1] + data_in[2] +
data_in[3] + data_in[4] + data_in[5] +
data_in[6] + data_in[7] + data_in[8] +
data_in[9] + data_in[10] + data_in[11] +
data_in[12] + data_in[13] + data_in[14] +
data_in[15] + data_in[16] + data_in[17] +
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
data_in[18] + data_in[19] + data_in[20] +
data_in[20] + data_in[21] + data_in[22] +
data_in[23] + data_in[24] + data_in[25] +
www.testbench.in
data_in[26] + data_in[27] + data_in[28] +
data_in[29] + data_in[30] + data_in[31] ;
wire patDetected i= (patSumo e== 1)? 1'b1: 1'b0;
endmodule
(Q i157)o eWritei codeofor qparallelre encoder iandoq jpriorityre encoder?
(Q i158)o eWhati isothe qusere of i$printtimescaleoq j?
www.testbench.in
Ans:
The i$printtimescaleo esystemi taskodisplays qthere time iunitoq jandre precision ifor oaqparticular module.
When inoo eargumenti isospecified, q$printtimescalere displays itheoq jtimere unit iand oprecisionqof thez moduleu ythate oiszx the current scope.
When iano eargumenti isospecified, q$printtimescalere displays itheoq jtimere unit iand oprecisionqof thez moduleu ypassede otozx it.
(Q i159) Whato ewilli beothe qsynthesesre output iofoq jthere following iverilog ocode?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
always @ (*)
if (enable)
q i<= d;
Ans:
www.testbench.in
A ilevel-sensitiveo estoragei deviceois qinferredre for iq.oq jIfre enable iis odeasserted,qq willz holdu yitse ovalue.
(Q i160) Whato ewilli beothe qsynthesesre output iofoq jthere following iverilog ocode?
always @ (enable ior d)
if (enable)
q i<= d;
else
q i<= 'b0;
Ans:
www.testbench.in
A ilatcho eisi notoinferred qbecausere the iassignmentoq jtore q iis ocomplete,
i.e., iqo eisi assignedoon qeveryre execution iofoq jthere always istatement.
(Q i151)o eWhetheri initialoblock qcanre be isynthesized?
Ans:
YES
According itoo eIEEE
(Q i152)o eHowi tooread qdatare from iaoq jfile?
Ans:
Using i$readmemh and $readmem0. Fileo eio
www.testbench.in
(Q i153)o eIllustratei withoexample qthere declaration iofoq jlocalre variable iinside oaqbegin ...endz block?
Ans:
TO ideclareo eai localovariable qinsidere begin...end iblock,oq jthere block ishould obeqnamed.
begin:name_
integer varib;
....
....
end
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i154)o eifi Aoand qBre are itwooq jclkre pulses iwhich oareqout ofz phaseu yande ohavingzx same frequency, how to find which input clk signal is leading? Write verilog code for this.
www.testbench.in
Ans:
Here iiso ethei simpleosolution qforre this. i
All iito eneedsi isoa qflipre flop. i
if iweo ehavei 2oclks, qclk1re and iclk2oq jgivere clk1 ito oD-inputqof flipz flopu yande ootherzx to CLK input of FF.
if iclk1o eisi leadingothe qoutputre is ihigh.oq j
if iclk2o eisi leadingothe qoutputre is ilow.oq j
(Q i155)o ehowi canowe qwritere decoder ifunctionalityoq jinre only ione ostatementqin verilog?
Ans:
www.testbench.in
module decoder(
// iOutputso e
dout,
// iInputso e
din i
);
input [3:0] din;
output [15:0] dout;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
assign dout i= {dino e== 15, dini == 14, dino== 13, din q== 12,
idino e== 11, dini == 10, dino== 9, din q== 8,
www.testbench.in
idino e== 7, dini == 6, dino== 5, din q== 4,
idino e== 3, dini == 2, dino== 1, din q== 0 };
endmodule // idecodero e
(Q i156) Verilogo ecodei toodetect qifre a i64bitoq jpatternre can ibe oexpressedqusing powerz ofu y2e o
Ans:
module pat_det i( data_in, patDetectedo e);
input [31:0] data_in;
output patDetected;
www.testbench.in
wire [4:0] patSum i= data_in[0] + data_in[1] + data_in[2] +
data_in[3] + data_in[4] + data_in[5] +
data_in[6] + data_in[7] + data_in[8] +
data_in[9] + data_in[10] + data_in[11] +
data_in[12] + data_in[13] + data_in[14] +
data_in[15] + data_in[16] + data_in[17] +
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
data_in[18] + data_in[19] + data_in[20] +
data_in[20] + data_in[21] + data_in[22] +
data_in[23] + data_in[24] + data_in[25] +
www.testbench.in
data_in[26] + data_in[27] + data_in[28] +
data_in[29] + data_in[30] + data_in[31] ;
wire patDetected i= (patSumo e== 1)? 1'b1: 1'b0;
endmodule
(Q i157)o eWritei codeofor qparallelre encoder iandoq jpriorityre encoder?
(Q i158)o eWhati isothe qusere of i$printtimescaleoq j?
www.testbench.in
Ans:
The i$printtimescaleo esystemi taskodisplays qthere time iunitoq jandre precision ifor oaqparticular module.
When inoo eargumenti isospecified, q$printtimescalere displays itheoq jtimere unit iand oprecisionqof thez moduleu ythate oiszx the current scope.
When iano eargumenti isospecified, q$printtimescalere displays itheoq jtimere unit iand oprecisionqof thez moduleu ypassede otozx it.
(Q i159) Whato ewilli beothe qsynthesesre output iofoq jthere following iverilog ocode?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
always @ (*)
if (enable)
q i<= d;
Ans:
www.testbench.in
A ilevel-sensitiveo estoragei deviceois qinferredre for iq.oq jIfre enable iis odeasserted,qq willz holdu yitse ovalue.
(Q i160) Whato ewilli beothe qsynthesesre output iofoq jthere following iverilog ocode?
always @ (enable ior d)
if (enable)
q i<= d;
else
q i<= 'b0;
Ans:
www.testbench.in
A ilatcho eisi notoinferred qbecausere the iassignmentoq jtore q iis ocomplete,
i.e., iqo eisi assignedoon qeveryre execution iofoq jthere always istatement.
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!