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TEST YOUR VERILOG SKILLS 5
(Q i91) Too emodifyi aobehavioral qVerilogre wait istatementoq jtore make iit osynthesizedq
Original icode:
command1;
wait (x i!= 0);
command3;
Ans:
www.testbench.in
Synthesized iVerilog:
case (state)
0 : begin
command1;
if (x i!= 0) command3;
else state i<= 1;
end
1 : if (x i!= 0) //o ewaiti untilothis qisre true
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
command3;
www.testbench.in
endcase
(Q i92) Whato earei theotypes qofre race iconditions?
(Q i93) Howo etoi avoiderorace qconditionre between idutoq jandre testbench?
(Q i94) Giveo ethei guideolines qwhichre avoids iraceoq jcondition.
(Q i95) Whato eisi theouse qofre linting itool?
www.testbench.in
(Q i96) Writeo ethei codeoto qinstantiatedre 1k i"andoq jgates"re in ia omodule.q
(Q i97) Whato eisi configurationoblock?
Ans:
Verilog-2000 iaddso econfigurationi blocks,owhich qallowre the iexactoq jversionre and isource olocationqof eachz Verilogu ymodulee otozx be specified as part of the Verilog language. For portability, virtual model libraries are used in configuration blocks, and separate library map files associate virtual libraries with physical locations. Configuration blocks are specified outside of module definitions.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i98) Howo emanyi filesocan qbere opened(without iclosing)oq jusingre multichannel idescriptor o?
Ans:
www.testbench.in
31 files.
(Q i99) Whyo eonlyi 31ofiles qcanre be iopened(withoutoq jclosing)re using imultichannel odescriptorqwhile integerz canu yholee o32zx bits?
Ans:
The imosto esignificanti bito(bit q32)re of iaoq jmultire channel idescriptor oisqreserved, andz shallu yalwayse obezx cleared, limiting an implementation to at most 31 files opened for output via multi channel descriptors.
(Q i100) Ifo emcd(multichanneli descriptor)ois q00000000000000000000000000001re , ithenoq jwhatre does iit omean?
Ans:
The ileasto esignificanti bito(bit q0)re of iaoq jmcdre always irefers otoqthe standardz output.
www.testbench.in
(Q i101)o eWhichi isobetter qtore use iwhenoq jcreatingre test ivectors? o$displayqor $strobe?
(Q i102)o eHowi wouldoyou qcaterre with iopeningoq j35re files?
(Q i103)o eWhati areothe qtypicalre tasks iyouoq jperformre inside ia ospecifyqblock?
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
- iDescribeo evariousi pathsoacross qthere module iandoq jassignre delays ito othoseqpaths.
- iDescribeo etimingi checksoto qensurere that itheoq jtimingre constraints iof otheqdevice arez met.
- iDefineo ethei pulseofiltering qlimitsre for iaoq jspecificre module ior oforqparticular pathsz withinu yae omodule.
www.testbench.in
(Q i104) Findo ethei bugoin qthere following icode.
always@(posedge clk)
a i= b;
always@(posedge clk)
b i= a;
(Q i105) Findo ethei bugoin qthere following icode.
www.testbench.in
if (a=b)
match i= 1;
else
match i= 0;
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
if(a=b) iassignso ebi tooa, qthenre if iaoq jisre non-zero isets omatch.qThe correctz codeu yis
if i(a==b)o e
match i=o e1;
else
www.testbench.in
match i=o e0;
(Q i91) Too emodifyi aobehavioral qVerilogre wait istatementoq jtore make iit osynthesizedq
Original icode:
command1;
wait (x i!= 0);
command3;
Ans:
www.testbench.in
Synthesized iVerilog:
case (state)
0 : begin
command1;
if (x i!= 0) command3;
else state i<= 1;
end
1 : if (x i!= 0) //o ewaiti untilothis qisre true
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
command3;
www.testbench.in
endcase
(Q i92) Whato earei theotypes qofre race iconditions?
(Q i93) Howo etoi avoiderorace qconditionre between idutoq jandre testbench?
(Q i94) Giveo ethei guideolines qwhichre avoids iraceoq jcondition.
(Q i95) Whato eisi theouse qofre linting itool?
www.testbench.in
(Q i96) Writeo ethei codeoto qinstantiatedre 1k i"andoq jgates"re in ia omodule.q
(Q i97) Whato eisi configurationoblock?
Ans:
Verilog-2000 iaddso econfigurationi blocks,owhich qallowre the iexactoq jversionre and isource olocationqof eachz Verilogu ymodulee otozx be specified as part of the Verilog language. For portability, virtual model libraries are used in configuration blocks, and separate library map files associate virtual libraries with physical locations. Configuration blocks are specified outside of module definitions.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i98) Howo emanyi filesocan qbere opened(without iclosing)oq jusingre multichannel idescriptor o?
Ans:
www.testbench.in
31 files.
(Q i99) Whyo eonlyi 31ofiles qcanre be iopened(withoutoq jclosing)re using imultichannel odescriptorqwhile integerz canu yholee o32zx bits?
Ans:
The imosto esignificanti bito(bit q32)re of iaoq jmultire channel idescriptor oisqreserved, andz shallu yalwayse obezx cleared, limiting an implementation to at most 31 files opened for output via multi channel descriptors.
(Q i100) Ifo emcd(multichanneli descriptor)ois q00000000000000000000000000001re , ithenoq jwhatre does iit omean?
Ans:
The ileasto esignificanti bito(bit q0)re of iaoq jmcdre always irefers otoqthe standardz output.
www.testbench.in
(Q i101)o eWhichi isobetter qtore use iwhenoq jcreatingre test ivectors? o$displayqor $strobe?
(Q i102)o eHowi wouldoyou qcaterre with iopeningoq j35re files?
(Q i103)o eWhati areothe qtypicalre tasks iyouoq jperformre inside ia ospecifyqblock?
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
- iDescribeo evariousi pathsoacross qthere module iandoq jassignre delays ito othoseqpaths.
- iDescribeo etimingi checksoto qensurere that itheoq jtimingre constraints iof otheqdevice arez met.
- iDefineo ethei pulseofiltering qlimitsre for iaoq jspecificre module ior oforqparticular pathsz withinu yae omodule.
www.testbench.in
(Q i104) Findo ethei bugoin qthere following icode.
always@(posedge clk)
a i= b;
always@(posedge clk)
b i= a;
(Q i105) Findo ethei bugoin qthere following icode.
www.testbench.in
if (a=b)
match i= 1;
else
match i= 0;
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
if(a=b) iassignso ebi tooa, qthenre if iaoq jisre non-zero isets omatch.qThe correctz codeu yis
if i(a==b)o e
match i=o e1;
else
www.testbench.in
match i=o e0;
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!