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Specman E
Interview Questions
TEST YOUR VERILOG SKILLS 4
(Q
i
65)
o
e
i
What
o
is
q
the
r
e
difference
i
between
o
q
j
$display
r
e
and
i
$strobe?
(Q
i
66)
o
e
i
What
o
is
q
the
r
e
difference
i
between
o
q
j
0
r
e
and
i
%z
o
format
q
specification?
Ans:
0
i
or
o
e
0
i
Unformatted
o
2
q
value
r
e
data
%z
i
or
o
e
%Z
i
Unformatted
o
4
q
value
r
e
data
(Q
i
67)
o
e
What
i
is
o
the
q
difference
r
e
between
i
0.000000e+00,0.000000
o
q
j
an
r
e
d0?
Ans:
www.testbench.in
0.000000e+00
i
or
o
e
0.000000E+00
i
Display
o
real
q
in
r
e
an
i
exponential
o
q
j
format
0.000000
i
or
o
e
0.000000
i
Display
o
real
q
in
r
e
a
i
decimal
o
q
j
format
0
i
or
o
e
0
i
Display
o
real
q
in
r
e
exponential
i
or
o
q
j
decimal
r
e
format,
i
whichever
o
format
q
results in
z
the
u
y
shorter
e
o
printed
z
x
output
(Q
i
68)
o
e
i
What
o
is
q
the
r
e
difference
i
between
o
q
j
$finish
r
e
ad
i
$stop?
The
i
$finish
o
e
system
i
task
o
simply
q
makes
r
e
the
i
simulator
o
q
j
exit
r
e
and
i
pass
o
control
q
back to
z
the
u
y
host
e
o
operating
z
x
system.
The
i
$stop
o
e
system
i
task
o
causes
q
simulation
r
e
to
i
be
o
q
j
suspended.
(Q
i
69)
o
e
i
What
o
is
q
the
r
e
difference
i
between
o
q
j
PLI
r
e
and
i
VPI?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
www.testbench.in
Verilog
i
Procedural
o
e
Interface
i
routines,
o
called
q
VPI
r
e
routines,
i
are
o
q
j
the
r
e
third
i
generation
o
of
q
the PLI.
(Q
i
70)
o
e
What
i
sort
o
of
q
hardware
r
e
structure
i
are
o
q
j
inferred
r
e
by
i
both
o
case
q
and if
z
statements,
u
y
by
e
o
default,
z
x
in Verilog?
(Q
i
71)
o
e
How
i
could
o
you
q
change
r
e
a
i
case
o
q
j
statement
r
e
in
i
order
o
that
q
its implementation
z
does
u
y
not
e
o
result
z
x
in a priority structure?
(Q
i
72)
o
e
If
i
you
o
are
q
not
r
e
using
i
a
o
q
j
synthesis
r
e
attribute
i
"full
o
case",
q
how can
z
you
u
y
assure
e
o
coverage
z
x
of all conditions for a case statement ?
(Q
i
73)
o
e
How
i
do
o
you
q
infer
r
e
tristate
i
gates
o
q
j
for
r
e
synthesis?
www.testbench.in
(Q
i
74)
o
e
Can
i
a
o
task
q
synthesized
r
e
?
(Q
i
75)
o
e
What
i
is
o
the
q
difference
r
e
between
i
$finish(0),
o
q
j
$finiash(1)
r
e
and
i
$finish(2)
o
?
Ans:
The
i
$finish
o
e
system
i
task
o
simply
q
makes
r
e
the
i
simulator
o
q
j
exit
r
e
and
i
pass
o
control
q
back to
z
the
u
y
host
e
o
operating
z
x
system.
If
i
an
o
e
expression
i
is
o
supplied
q
to
r
e
this
i
task,
o
q
j
then
r
e
its
i
value
o
(0,
q
1, or
z
2)
u
y
determines
e
o
the
z
x
diagnostic messages that
are
i
printed
o
e
before
i
the
o
prompt
q
is
r
e
issued.
i
If
o
q
j
no
r
e
argument
i
is
o
supplied,
q
then a
z
value
u
y
of
e
o
1
z
x
is taken as the default.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
$finish(0)
i
Prints
o
e
nothing
$finish(1)
i
Prints
o
e
simulation
i
time
o
and
q
location
www.testbench.in
$finish(2)
i
Prints
o
e
simulation
i
time,
o
location,
q
and
r
e
statistics
i
about
o
q
j
the
r
e
memory
i
and
o
CPU
q
time used
z
in
u
y
simulation
(Q
i
76)
o
e
i
What
o
is
q
the
r
e
difference
i
b/w
o
q
j
$time
r
e
,
i
$stime
o
and
q
$realtime ?
Ans:
The
i
$time
o
e
system
i
function
o
returns
q
an
r
e
integer
i
that
o
q
j
is
r
e
a
i
64-bit
o
time,
q
scaled to
z
the
u
y
timescale
e
o
unit
z
x
of the module that invoked it.
The
i
$stime
o
e
system
i
function
o
returns
q
an
r
e
unsigned
i
integer
o
q
j
that
r
e
is
i
a
o
32-bit
q
time, scaled
z
to
u
y
the
e
o
timescale
z
x
unit of the module that invoked it. If the actual simulation time does not fit in 32 bits, the low order 32 bits of the current simulation time are returned.
The
i
$realtime
o
e
system
i
function
o
returns
q
a
r
e
real
i
number
o
q
j
time
r
e
that,
i
like
o
$time,
q
is scaled
z
to
u
y
the
e
o
time
z
x
unit of the module that invoked it.
www.testbench.in
(Q
i
77)
o
e
i
Difference
o
between
q
!
r
e
And
i
~
o
q
j
?
(Q
i
78)
o
e
i
What
o
is
q
the
r
e
difference
i
between
o
q
j
$test$plusargs
r
e
and
i
$value$plusargs
o
?
(Q
i
79)
o
e
i
What
o
is
q
the
r
e
difference
i
Difference
o
q
j
between
r
e
the
i
two
o
statement
q
? Whether
z
a
u
y
and
e
o
b
z
x
values are equal?
reg
i
[
1
:
0
]
o
e
data
;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
a
i
=
o
e
data
[
0
]
i
||
o
data
[
1
];
b
i
=
o
e
|
data
;
www.testbench.in
(Q
i
80)
o
e
i
What
o
is
q
the
r
e
difference
i
between
o
q
j
the
r
e
following
i
two
o
programs?
a
)
initial
i
o
e
#
10
i
a
o
=
0
;
always
@(
a
)
a
<=
i
~
a
;
b
)
initial
#
10
i
a
o
e
=
0
;
www.testbench.in
always
@(
a
)
a
i
=
o
e
~
a
;
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
When
i
"a=~a"
o
e
is
i
evaluated
o
and
q
'a'
r
e
is
i
updated,
o
q
j
clearly
r
e
you
i
must
o
agree
q
that execution
z
is
u
y
*not*
e
o
stalled
z
x
at the @a event control. | When execution reaches the @a event control, 'a' has already changed. | It will not change again. | So the event control will stall forever; its event of interest has already occurred, earlier in the same time slot, and can no longer have any effect.
(Q
i
81)
o
e
i
what
o
is/are
q
the
r
e
differences
i
between
o
q
j
SIMULATION
r
e
and
i
SYNTHESIS
o
Ans:
www.testbench.in
Simulation
i
<=
o
e
verify
i
your
o
design.
q
synthesis
i
<=
o
e
Check
i
for
o
your
q
timing
r
e
Simulation
i
is
o
e
used
i
to
o
verify
q
the
r
e
functionality
i
of
o
q
j
the
r
e
circuit..
i
a)Functional
o
Simulation:study
q
of ckt's
z
operation
u
y
independent
e
o
of
z
x
timing parameters and gate delays. b) Timing Simulation :study including estimated delays, verify setup,hold and other timing requirements of devices like flip flops are met.
Synthesis:One
i
of
o
e
the
i
foremost
o
in
q
back
r
e
end
i
steps
o
q
j
where
r
e
by
i
synthesizing
o
is
q
nothing but
z
converting
u
y
VHDL
e
o
or
z
x
VERILOG description to a set of primitives(equations as in CPLD) or components(as in FPGA'S)to fit into the target technology. Basically the synthesis tools convert the design description into equations or components .
(Q
i
82)
o
e
i
What
o
is
q
the
r
e
different
i
between
o
q
j
$setup
r
e
and
i
$display?
Ans:
$setup
i
is
o
e
a
i
timing
o
check
q
task
r
e
and
i
$display
o
q
j
is
r
e
system
i
task.
www.testbench.in
Only
i
System
o
e
tasks
i
and
o
function
q
can
r
e
be
i
overridden.
o
q
j
Timing
r
e
check
i
tasks
o
cannot
q
be overridden.
i.e.
i
User
o
e
can
i
change
o
the
q
definition
r
e
of
i
the
o
q
j
$display
r
e
but
i
not
o
$setup.
(Q
i
83)
o
e
i
What
o
is
q
the
r
e
difference
i
between
o
q
j
parameter
r
e
and
i
local
o
parameter?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
84)
o
e
i
Why
o
is
q
it
r
e
recommended
i
not
o
q
j
to
r
e
mix
i
blocking
o
and
q
non-blocking assignments
z
in
u
y
the
e
o
same
z
x
block?
(Q
i
85)
o
e
i
Declare
o
parameters
q
for
r
e
representing
i
the
o
q
j
state
r
e
machine
i
states
o
using
q
one hot
z
encoding.
(Q
i
86)
o
e
What
i
does
o
a
q
function
r
e
synthesize
i
to?
www.testbench.in
(Q
i
87)
o
e
How
i
to
o
change
q
the
r
e
value
i
of
o
q
j
width
r
e
to
i
3
o
in
q
the following
z
code
u
y
?
`define
i
width
o
e
7
(Q
i
88)
o
e
What
i
is
o
the
q
functionality
r
e
of
i
$input
o
q
j
?
Ans:
The
i
$input
o
e
system
i
task
o
allows
q
command
r
e
input
i
text
o
q
j
to
r
e
come
i
from
o
a
q
named file
z
instead
u
y
of
e
o
from
z
x
the terminal. At the end of the command file, the input is switched back to the terminal.
www.testbench.in
(Q
i
89)
o
e
What
i
is
o
the
q
MCD
r
e
value
i
of
o
q
j
STD
r
e
OUTPUT
i
?
0000000000000000000000000000001
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q
i
90)
o
e
i
What
o
is
q
the
r
e
difference
i
between
o
q
j
blocking
r
e
and
i
non
o
blocking?
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
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