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TEST YOUR VERILOG SKILLS 4
(Q i65) Whato eisi theodifference qbetweenre $display iandoq j$strobe?
(Q i66) Whato eisi theodifference qbetweenre 0 iandoq j%zre format ispecification?
Ans:
0 ioro e0i Unformattedo2 qvaluere data
%z ioro e%Zi Unformattedo4 qvaluere data
(Q i67)o eWhati isothe qdifferencere between i0.000000e+00,0.000000oq janre d0?
Ans:
www.testbench.in
0.000000e+00 ioro e0.000000E+00i Displayoreal qinre an iexponentialoq jformat
0.000000 ioro e0.000000i Displayoreal qinre a idecimaloq jformat
0 ioro e0i Displayoreal qinre exponential ioroq jdecimalre format, iwhichever oformatqresults inz theu yshortere oprintedzx output
(Q i68) Whato eisi theodifference qbetweenre $finish iadoq j$stop?
The i$finisho esystemi taskosimply qmakesre the isimulatoroq jexitre and ipass ocontrolqback toz theu yhoste ooperatingzx system.
The i$stopo esystemi taskocauses qsimulationre to ibeoq jsuspended.
(Q i69) Whato eisi theodifference qbetweenre PLI iandoq jVPI?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
www.testbench.in
Verilog iProceduralo eInterfacei routines,ocalled qVPIre routines, iareoq jthere third igeneration oofqthe PLI.
(Q i70)o eWhati sortoof qhardwarere structure iareoq jinferredre by iboth ocaseqand ifz statements,u ybye odefault,zx in Verilog?
(Q i71)o eHowi couldoyou qchangere a icaseoq jstatementre in iorder othatqits implementationz doesu ynote oresultzx in a priority structure?
(Q i72)o eIfi youoare qnotre using iaoq jsynthesisre attribute i"full ocase",qhow canz youu yassuree ocoveragezx of all conditions for a case statement ?
(Q i73)o eHowi dooyou qinferre tristate igatesoq jforre synthesis?
www.testbench.in
(Q i74)o eCani aotask qsynthesizedre ?
(Q i75)o eWhati isothe qdifferencere between i$finish(0),oq j$finiash(1)re and i$finish(2) o?
Ans:
The i$finisho esystemi taskosimply qmakesre the isimulatoroq jexitre and ipass ocontrolqback toz theu yhoste ooperatingzx system.
If iano eexpressioni isosupplied qtore this itask,oq jthenre its ivalue o(0,q1, orz 2)u ydeterminese othezx diagnostic messages that
are iprintedo ebeforei theoprompt qisre issued. iIfoq jnore argument iis osupplied,qthen az valueu yofe o1zx is taken as the default.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
$finish(0) iPrintso enothing
$finish(1) iPrintso esimulationi timeoand qlocation
www.testbench.in
$finish(2) iPrintso esimulationi time,olocation, qandre statistics iaboutoq jthere memory iand oCPUqtime usedz inu ysimulation
(Q i76) Whato eisi theodifference qb/wre $time i,oq j$stimere and i$realtime o?
Ans:
The i$timeo esystemi functionoreturns qanre integer ithatoq jisre a i64-bit otime,qscaled toz theu ytimescalee ounitzx of the module that invoked it.
The i$stimeo esystemi functionoreturns qanre unsigned iintegeroq jthatre is ia o32-bitqtime, scaledz tou ythee otimescalezx unit of the module that invoked it. If the actual simulation time does not fit in 32 bits, the low order 32 bits of the current simulation time are returned.
The i$realtimeo esystemi functionoreturns qare real inumberoq jtimere that, ilike o$time,qis scaledz tou ythee otimezx unit of the module that invoked it.
www.testbench.in
(Q i77) Differenceo ebetweeni !oAnd q~re ?
(Q i78) Whato eisi theodifference qbetweenre $test$plusargs iandoq j$value$plusargsre ?
(Q i79) Whato eisi theodifference qDifferencere between itheoq jtwore statement i? oWhetherqa andz bu yvaluese oarezx equal?
reg [1:0] data;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
a i= data[0] || data[1];
b i= |data;
www.testbench.in
(Q i80) Whato eisi theodifference qbetweenre the ifollowingoq jtwore programs?
a)initial
#10 a i=0;
always@(a)
a<= ~a;
b)initial
#10 a i=0;
www.testbench.in
always@(a)
a i= ~a;
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
When i"a=~a"o eisi evaluatedoand q'a're is iupdated,oq jclearlyre you imust oagreeqthat executionz isu y*not*e ostalledzx at the @a event control. Â When execution reaches the @a event control, 'a' has already changed. Â It will not change again. Â So the event control will stall forever; its event of interest has already occurred, earlier in the same time slot, and can no longer have any effect.
(Q i81) whato eis/arei theodifferences qbetweenre SIMULATION iandoq jSYNTHESISre
Ans:
www.testbench.in
Simulation i<=o everifyi yourodesign. q
synthesis i<=o eChecki foroyour qtimingre
Simulation iiso eusedi tooverify qthere functionality iofoq jthere circuit.. ia)Functional oSimulation:studyqof ckt'sz operationu yindependente oofzx timing parameters and gate delays. b) Timing Simulation :study including estimated delays, verify setup,hold and other timing requirements of devices like flip flops are met.
Synthesis:One iofo ethei foremostoin qbackre end istepsoq jwherere by isynthesizing oisqnothing butz convertingu yVHDLe oorzx VERILOG description to a set of primitives(equations as in CPLD) or components(as in FPGA'S)to fit into the target technology. Basically the synthesis tools convert the design description into equations or components .
(Q i82) Whato eisi theodifferent qbetweenre $setup iandoq j$display?
Ans:
$setup iiso eai timingocheck qtaskre and i$displayoq jisre system itask.
www.testbench.in
Only iSystemo etasksi andofunction qcanre be ioverridden.oq jTimingre check itasks ocannotqbe overridden.
i.e. iUsero ecani changeothe qdefinitionre of itheoq j$displayre but inot o$setup.
(Q i83) Whato eisi theodifference qbetweenre parameter iandoq jlocalre parameter?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i84) Whyo eisi itorecommended qnotre to imixoq jblockingre and inon-blocking oassignmentsqin thez sameu yblock?
(Q i85) Declareo eparametersi fororepresenting qthere state imachineoq jstatesre using ione ohotqencoding.
(Q i86)o eWhati doesoa qfunctionre synthesize ito?
www.testbench.in
(Q i87)o eHowi toochange qthere value iofoq jwidthre to i3 oinqthe followingz codeu y?
`define width i7
(Q i88)o eWhati isothe qfunctionalityre of i$inputoq j?
Ans:
The i$inputo esystemi taskoallows qcommandre input itextoq jtore come ifrom oaqnamed filez insteadu yofe ofromzx the terminal. At the end of the command file, the input is switched back to the terminal.
www.testbench.in
(Q i89)o eWhati isothe qMCDre value iofoq jSTDre OUTPUT i?
0000000000000000000000000000001
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i90) Whato eisi theodifference qbetweenre blocking iandoq jnonre blocking?
(Q i65) Whato eisi theodifference qbetweenre $display iandoq j$strobe?
(Q i66) Whato eisi theodifference qbetweenre 0 iandoq j%zre format ispecification?
Ans:
0 ioro e0i Unformattedo2 qvaluere data
%z ioro e%Zi Unformattedo4 qvaluere data
(Q i67)o eWhati isothe qdifferencere between i0.000000e+00,0.000000oq janre d0?
Ans:
www.testbench.in
0.000000e+00 ioro e0.000000E+00i Displayoreal qinre an iexponentialoq jformat
0.000000 ioro e0.000000i Displayoreal qinre a idecimaloq jformat
0 ioro e0i Displayoreal qinre exponential ioroq jdecimalre format, iwhichever oformatqresults inz theu yshortere oprintedzx output
(Q i68) Whato eisi theodifference qbetweenre $finish iadoq j$stop?
The i$finisho esystemi taskosimply qmakesre the isimulatoroq jexitre and ipass ocontrolqback toz theu yhoste ooperatingzx system.
The i$stopo esystemi taskocauses qsimulationre to ibeoq jsuspended.
(Q i69) Whato eisi theodifference qbetweenre PLI iandoq jVPI?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
www.testbench.in
Verilog iProceduralo eInterfacei routines,ocalled qVPIre routines, iareoq jthere third igeneration oofqthe PLI.
(Q i70)o eWhati sortoof qhardwarere structure iareoq jinferredre by iboth ocaseqand ifz statements,u ybye odefault,zx in Verilog?
(Q i71)o eHowi couldoyou qchangere a icaseoq jstatementre in iorder othatqits implementationz doesu ynote oresultzx in a priority structure?
(Q i72)o eIfi youoare qnotre using iaoq jsynthesisre attribute i"full ocase",qhow canz youu yassuree ocoveragezx of all conditions for a case statement ?
(Q i73)o eHowi dooyou qinferre tristate igatesoq jforre synthesis?
www.testbench.in
(Q i74)o eCani aotask qsynthesizedre ?
(Q i75)o eWhati isothe qdifferencere between i$finish(0),oq j$finiash(1)re and i$finish(2) o?
Ans:
The i$finisho esystemi taskosimply qmakesre the isimulatoroq jexitre and ipass ocontrolqback toz theu yhoste ooperatingzx system.
If iano eexpressioni isosupplied qtore this itask,oq jthenre its ivalue o(0,q1, orz 2)u ydeterminese othezx diagnostic messages that
are iprintedo ebeforei theoprompt qisre issued. iIfoq jnore argument iis osupplied,qthen az valueu yofe o1zx is taken as the default.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
$finish(0) iPrintso enothing
$finish(1) iPrintso esimulationi timeoand qlocation
www.testbench.in
$finish(2) iPrintso esimulationi time,olocation, qandre statistics iaboutoq jthere memory iand oCPUqtime usedz inu ysimulation
(Q i76) Whato eisi theodifference qb/wre $time i,oq j$stimere and i$realtime o?
Ans:
The i$timeo esystemi functionoreturns qanre integer ithatoq jisre a i64-bit otime,qscaled toz theu ytimescalee ounitzx of the module that invoked it.
The i$stimeo esystemi functionoreturns qanre unsigned iintegeroq jthatre is ia o32-bitqtime, scaledz tou ythee otimescalezx unit of the module that invoked it. If the actual simulation time does not fit in 32 bits, the low order 32 bits of the current simulation time are returned.
The i$realtimeo esystemi functionoreturns qare real inumberoq jtimere that, ilike o$time,qis scaledz tou ythee otimezx unit of the module that invoked it.
www.testbench.in
(Q i77) Differenceo ebetweeni !oAnd q~re ?
(Q i78) Whato eisi theodifference qbetweenre $test$plusargs iandoq j$value$plusargsre ?
(Q i79) Whato eisi theodifference qDifferencere between itheoq jtwore statement i? oWhetherqa andz bu yvaluese oarezx equal?
reg [1:0] data;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
a i= data[0] || data[1];
b i= |data;
www.testbench.in
(Q i80) Whato eisi theodifference qbetweenre the ifollowingoq jtwore programs?
a)initial
#10 a i=0;
always@(a)
a<= ~a;
b)initial
#10 a i=0;
www.testbench.in
always@(a)
a i= ~a;
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
When i"a=~a"o eisi evaluatedoand q'a're is iupdated,oq jclearlyre you imust oagreeqthat executionz isu y*not*e ostalledzx at the @a event control. Â When execution reaches the @a event control, 'a' has already changed. Â It will not change again. Â So the event control will stall forever; its event of interest has already occurred, earlier in the same time slot, and can no longer have any effect.
(Q i81) whato eis/arei theodifferences qbetweenre SIMULATION iandoq jSYNTHESISre
Ans:
www.testbench.in
Simulation i<=o everifyi yourodesign. q
synthesis i<=o eChecki foroyour qtimingre
Simulation iiso eusedi tooverify qthere functionality iofoq jthere circuit.. ia)Functional oSimulation:studyqof ckt'sz operationu yindependente oofzx timing parameters and gate delays. b) Timing Simulation :study including estimated delays, verify setup,hold and other timing requirements of devices like flip flops are met.
Synthesis:One iofo ethei foremostoin qbackre end istepsoq jwherere by isynthesizing oisqnothing butz convertingu yVHDLe oorzx VERILOG description to a set of primitives(equations as in CPLD) or components(as in FPGA'S)to fit into the target technology. Basically the synthesis tools convert the design description into equations or components .
(Q i82) Whato eisi theodifferent qbetweenre $setup iandoq j$display?
Ans:
$setup iiso eai timingocheck qtaskre and i$displayoq jisre system itask.
www.testbench.in
Only iSystemo etasksi andofunction qcanre be ioverridden.oq jTimingre check itasks ocannotqbe overridden.
i.e. iUsero ecani changeothe qdefinitionre of itheoq j$displayre but inot o$setup.
(Q i83) Whato eisi theodifference qbetweenre parameter iandoq jlocalre parameter?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i84) Whyo eisi itorecommended qnotre to imixoq jblockingre and inon-blocking oassignmentsqin thez sameu yblock?
(Q i85) Declareo eparametersi fororepresenting qthere state imachineoq jstatesre using ione ohotqencoding.
(Q i86)o eWhati doesoa qfunctionre synthesize ito?
www.testbench.in
(Q i87)o eHowi toochange qthere value iofoq jwidthre to i3 oinqthe followingz codeu y?
`define width i7
(Q i88)o eWhati isothe qfunctionalityre of i$inputoq j?
Ans:
The i$inputo esystemi taskoallows qcommandre input itextoq jtore come ifrom oaqnamed filez insteadu yofe ofromzx the terminal. At the end of the command file, the input is switched back to the terminal.
www.testbench.in
(Q i89)o eWhati isothe qMCDre value iofoq jSTDre OUTPUT i?
0000000000000000000000000000001
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i90) Whato eisi theodifference qbetweenre blocking iandoq jnonre blocking?
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!