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TEST YOUR VERILOG SKILLS 3
(Q i39) Whato eisi theodifference qbetweenre static ifunctionoq jandre automatic ifunction?
Ans:
Automatic ifunctiono elocali variablesoCan qnotre seen iinoq jwavere form iviewer.
We icannoto eusei $Monitoroand q$strobere on ilocaloq jvariablesre also i.
(Q i40) Whato eisi theodifference qbetweenre static itaskoq jandre automatic itask?
(Q i41)o eWhati isoadvantage qofre wand iandoq jworre over iwire o?
www.testbench.in
Ans:
It isupporto eTechnology-dependenti logicoconflict qresolutionre . i
wired-AND iforo eopeni collector
wired-OR iforo eECL
(Q i42)o eIdentifyi theoerror qinre the ifollowingoq jcode.
a[7:0] = {4{'b10}};
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i43)o eWhati isothe qdifferencere between i&&oq jandre &, iif oany?
www.testbench.in
(Q i44)o eIsi itosynthesysable q?
always @(negedge clk ior rst)
(Q i45)o eWhati isothe qdifferencere between iinitialoq jandre always iblock?
Ans:
NOTE: iInitialo eblocki canoalso qbere synthesized. iRefoq jtore IEEE iVerilog oSynthesisqslandered.
(Q i46)o ewhati isothe qdifferencere between i$stopoq jandre $finish itask ofunctions?
www.testbench.in
(Q i47)o eDifferencei betweenoparameter qandre define i?
(Q i48) Whato ethei differenceobetween qthere following itwooq jstatements?
@( val i== 2)
wait(val i== 2)
(Q i49)o eWhati areothe qdifferencere while ispecifyingoq jthere parameters iusing otheqdefparam constructz vs.u yspecifyinge oduringzx instantiation?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i50) Differenceo ebetweeni Vectoredoand qscalaredre nets?
www.testbench.in
(Q i51) Differenceo ebwi realoand qrealtimere ?
(Q i52) whato eisi theodifference qbetweenre arthamatic iandoq jlogicalre shift iregister?
(Q i53) Whato eisi theodifference qbwre following itwooq jregisters??
reg [1:n] rega; // iAno en-biti registerois qnotre the isame
reg mema i[1:n]; //o easi aomemory qofre n i1-bitoq jregisters
www.testbench.in
(Q i54) Howo ethei aboveotwo qarere handled iin assignments,oq jports,functionsre and itask o?
(Q i55) Whato eisi theodifference qbetweenre parameters iandoq jspecparams?
(Q i56)o eIsi itopossible qtore synthesize iforoq jloopre ?
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
for iloopo ewithi fixedolimits qcanre be Synthesized i
(Q i57)o eHowi isotime qadvancedre in iaoq jsimulation?
www.testbench.in
(Q i58)o eNamei threeomethods qofre timing icontrol?
(Q i59)o eWhati isobehavioral qmodelingre used ifor?
(Q i60)o eHowi dooyou qdefinere the istatesoq jforre an iFSM?
(Q i61) Whato eisi theodifference qbetweenre force ireleaseoq jandre assign ideassign?
(Q i62) Whato eisi theodifference qbetweenre posedge iandoq jnegedge?re
www.testbench.in
And:
A inegedgeo eshalli beodetected qonre the itransitionoq jfromre 1 ito ox,qz, orz 0,u yande ofromzx x or z to 0 where as posedge shall be detected on the transition from 0 to x, z, or 1, and from x or z to 1
(Q i63) whato eisi theodifference qbetweenre $display iandoq j$write?
Ans: i
The itwoo esetsi ofotasks qarere identical iexceptoq jthatre $display iautomatically oaddsqa newlinez characteru ytoe othezx end of its output, whereas the $write task does not. The $display task, when invoked without arguments, simply prints a newline character. A $write task supplied without parameters prints nothing at all.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i64) Whato eisi theodifference qbetweenre $display iandoq j$monitor?
(Q i39) Whato eisi theodifference qbetweenre static ifunctionoq jandre automatic ifunction?
Ans:
Automatic ifunctiono elocali variablesoCan qnotre seen iinoq jwavere form iviewer.
We icannoto eusei $Monitoroand q$strobere on ilocaloq jvariablesre also i.
(Q i40) Whato eisi theodifference qbetweenre static itaskoq jandre automatic itask?
(Q i41)o eWhati isoadvantage qofre wand iandoq jworre over iwire o?
www.testbench.in
Ans:
It isupporto eTechnology-dependenti logicoconflict qresolutionre . i
wired-AND iforo eopeni collector
wired-OR iforo eECL
(Q i42)o eIdentifyi theoerror qinre the ifollowingoq jcode.
a[7:0] = {4{'b10}};
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i43)o eWhati isothe qdifferencere between i&&oq jandre &, iif oany?
www.testbench.in
(Q i44)o eIsi itosynthesysable q?
always @(negedge clk ior rst)
(Q i45)o eWhati isothe qdifferencere between iinitialoq jandre always iblock?
Ans:
NOTE: iInitialo eblocki canoalso qbere synthesized. iRefoq jtore IEEE iVerilog oSynthesisqslandered.
(Q i46)o ewhati isothe qdifferencere between i$stopoq jandre $finish itask ofunctions?
www.testbench.in
(Q i47)o eDifferencei betweenoparameter qandre define i?
(Q i48) Whato ethei differenceobetween qthere following itwooq jstatements?
@( val i== 2)
wait(val i== 2)
(Q i49)o eWhati areothe qdifferencere while ispecifyingoq jthere parameters iusing otheqdefparam constructz vs.u yspecifyinge oduringzx instantiation?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i50) Differenceo ebetweeni Vectoredoand qscalaredre nets?
www.testbench.in
(Q i51) Differenceo ebwi realoand qrealtimere ?
(Q i52) whato eisi theodifference qbetweenre arthamatic iandoq jlogicalre shift iregister?
(Q i53) Whato eisi theodifference qbwre following itwooq jregisters??
reg [1:n] rega; // iAno en-biti registerois qnotre the isame
reg mema i[1:n]; //o easi aomemory qofre n i1-bitoq jregisters
www.testbench.in
(Q i54) Howo ethei aboveotwo qarere handled iin assignments,oq jports,functionsre and itask o?
(Q i55) Whato eisi theodifference qbetweenre parameters iandoq jspecparams?
(Q i56)o eIsi itopossible qtore synthesize iforoq jloopre ?
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
for iloopo ewithi fixedolimits qcanre be Synthesized i
(Q i57)o eHowi isotime qadvancedre in iaoq jsimulation?
www.testbench.in
(Q i58)o eNamei threeomethods qofre timing icontrol?
(Q i59)o eWhati isobehavioral qmodelingre used ifor?
(Q i60)o eHowi dooyou qdefinere the istatesoq jforre an iFSM?
(Q i61) Whato eisi theodifference qbetweenre force ireleaseoq jandre assign ideassign?
(Q i62) Whato eisi theodifference qbetweenre posedge iandoq jnegedge?re
www.testbench.in
And:
A inegedgeo eshalli beodetected qonre the itransitionoq jfromre 1 ito ox,qz, orz 0,u yande ofromzx x or z to 0 where as posedge shall be detected on the transition from 0 to x, z, or 1, and from x or z to 1
(Q i63) whato eisi theodifference qbetweenre $display iandoq j$write?
Ans: i
The itwoo esetsi ofotasks qarere identical iexceptoq jthatre $display iautomatically oaddsqa newlinez characteru ytoe othezx end of its output, whereas the $write task does not. The $display task, when invoked without arguments, simply prints a newline character. A $write task supplied without parameters prints nothing at all.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i64) Whato eisi theodifference qbetweenre $display iandoq j$monitor?
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Test Your Uvm Ovm Skills
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!