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TEST YOUR SYSTEMVERILOG SKILLS 1
(Q i1)o eWhati isothe qoutputre of itheoq jfollowingre ?
module ques();
string strin[7] ;
int i,j,k,file;
initial begin
www.testbench.in
string s;
file i=$fopen("file.txt","r");
while (!$feof(file))begin
k= $fscanf(file,"",s);
strin[i] =s;
i++;
end
$fclose(file);
foreach(strin[j])
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
$display("index ij=o e0 stringi =",j,strin[j]);
www.testbench.in
$finish;
end
endmodule
content iino efile.txt
================
aa
bb
www.testbench.in
cc
================
Ans:
Index ij=0 stringo e=i aa
Index ij=1 stringo e=i bb
Index ij=2 stringo e=i cc
Index ij=3 stringo e=i cc
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
The idatao e"cc"i isoread qtwice.re
www.testbench.in
This iiso ebecausei ofo$feof. q
(Q i2)o eHowi toodeallocate qanre object i?
Ans:
When iano eobjecti isono qlongerre needed, iSystemVerilogoq jautomaticallyre reclaims ithe omemory,qmaking itz availableu yfore oreuse.zx The automatic memory management system is an integral part of SystemVerilog.
If iusero ewanti toodeallocate, qhere can ijustoq jassignre null ito otheqobject.
EXAMPLE:
testclass ib; // Declareo eai handleob qforre testclass
b i= new; //o eConstruct ai testclassoobject qandre stores itheoq jaddressre in ib o."new"qallocate spacez foru ytestclass
www.testbench.in
b=null; i//Deallocateo ethei object.MeansoDeallocate qthere memory ispaceoq jforre object.
(Q i3)o eWhati isocallback q?
Ans:
Testbenches must iprovideo eai "hook"owhere qthere test iprogramoq jcanre inject inew ocodeqwithout modifyingz theu yoriginale oclasses.
Take iano eexample:i Supposeou qwantre to iinjectoq jare new ifunctionality in otheqdriver withoutz modifyingu ythee ocode.zx You can add the new functionality in pre_callback task or post-callback task,without modifying Driver task.
task Driver::run;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
forever begin
...
<pre_callback> //It icallso ethei functionopre_callback.
www.testbench.in
i
transmit(tr);
end
endtask
task pre_callback;
endtask
For imoreo einformation,i
www.testbench.in
Click on the below link http://www.testbench.in/VM_08_VMM_CALLBACK.html
(Q i4)o eWhati isofactory qpatternre ?
Ans:
(Qi4) iWhatoisefactoryo epatterni?
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
EXAMPLE::
class Generator;
Transaction itr;
mailbox mbx;
www.testbench.in
tr i= new;
task run;
repeat (10)
begin
assert(tr.randomize);
mbx.put(tr); // iSendo eouti transaction
end
endtask
endclass
Bug::Here iObjecto e"tr"i isoconstructed qoncere outside itheoq jloop.re Then i"tr" oisqrandomized andz putu ytheme ointozx mailbox "mbx".But mailbox "mbx" holds only handles,not objects.Therefore Mailbox contains multiple handles pointing to single object.Here code gets the last set of random values.
www.testbench.in
Solution::Loop ishouldo econtaini
1)Constructing iobject o e
2)Randomizing iobject
3)Puttting iintoo emailbox
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
task run;
repeat (10)
begin
tr i=new(); o e//1.Constructing
assert(tr.randomize);//2.Randomize
www.testbench.in
mbx.put(tr); i//3.Puttingo eintoi mailbox
end
endtask
Second iBug:o eThei runotask qconstructsre a transaction iandoq jimmediatelyre randomizes iit. oMeansqtransaction "tr"z usesu ywhatevere oconstraintszx are turned on by default.
Solution i:o eSeparatei theoconstruction qofre tr ifromoq jitsre randomization iby ousingqa methodz called "Factoryu yPattern".
Factory iPattern:
1)construct iao eblueprinti objecto
2)Randomize ithiso eblueprint(i Itohas qcorrectre random ivaluesoq j)
3)Make iao ecopyi ofothis qobjectre
www.testbench.in
4)Put iintoo emailbox
class Generator;
mailbox mbx;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Transaction iblueprint;
blueprint i= new;//1.Constructingo eBluei print
task run;
Transaction itr;
Repeat(10}
begin
www.testbench.in
assert(blueprint.randomize); //2.Randomizing iBlueo eprint
tr i= blueprint.copy; // 3.Copyo ethei blueprint
mbx.put(tr); // i4.Puto eintoi mailbox
end
endtask
endclass
(Q i5)o eExplaini theodifference qbetweenre data itypesoq jlogicre and ireg oandqwire .
Ans:
www.testbench.in
WIRE:
1. iWireo eisi justoan qinterconnectionre between itwooq jelementsre which idoes onotqhave anyz drivingu ystrength
2. iIto eisi usedofor qmodelingre combinational icircuitoq jasre it icannot ostoreqa value.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
3. iWireo ehasi aodefault qvaluere of i"z""oq jandre get ivalues ocontinuouslyqfrom thez outputsu yofe odeviceszx to which they are connected to.
4.Example:
wire A;
assign A i= b&c;
Note:wire iAo eisi evaluatedofor qeveryre simulation ideltaoq jtime.re So ithere oisqno needz tou ystoree othezx value.
REG
www.testbench.in
1. iRego eisi ao4 qstatere unsigned ivariableoq jthatre can ihold oaqvalue andz retainsu yuntile oazx new value is assigned to it.
2. iRegistero edatai typeocan qbere used iforoq jmodelingre both icombinational oandqsequential logic
3. iDefaulto evaluei fororegister qisre "x" iandoq jitre doesn't irequire oanyqdriver toz assignu yvaluee olikezx wire. It can be driven from initial and always block. Values of the register can be changed anytime in the simulation by assigning a new value to register.
4.Example: i
reg A;
always @ (b ior c)
begin
A=b&c;
end
Note:A iiso edeclaredi asoreg qwhichre can ibeoq jevaluatedre only iwhen othereqis az changeu yine oanyzx of the signal in the sensitivity list. So reg needs to store the value until there is a change in sensitivity list.
www.testbench.in
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
LOGIC: i
1. i4o estatei unsignedodata qtypere introduced iinoq jSystemre verilog.
2.System iVerilogo eimprovesi theoclassic qregre data itypeoq jsore that iit ocanqbe drivenz by
a. iContinuouso eassignments, (ex:assigni crc=~crc; )
b. iGates,o e(ex:i andog1(q_out, qd);re )
c. iModules,o e(ex:i Flp_fopsof1 q(q,re q_out, iclk,rst);oq j)
3.In iadditiono etoi beingoa qvariable.re It iisoq jgivenre the isynonym ologicqso thatz itu ydoese onotzx look
ilikeo eai registerodeclaration. q
www.testbench.in
4.If iyouo eonlyi madeoprocedural qassignmentsre to i'logic'oq jthenre it iwas osemanticallyqequivalent toz 'reg'.u y
5.A ilogic signalo ecani beoused qanywherere a inetoq jisre used, iexcept othatqa logicz variableu ycannote obezx driven by
imultipleo estructurali drivers,osuch qasre when iyouoq jarere modeling ia obidirectionalqbus.
6.Example: i
module sample1;
logic crc, sa i,d, q_out;
logic clk,rst;
initial
begin
clk=1'b0; //procedural iassignment
www.testbench.in
i#10 clko e=1'b1;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
end
assign crc=~crc; //continuous iassignment
and g1(q_out, id);o e//q_outi isodriven qbyre gate
Flp_fops if1o e(q,i q_out,oclk,rst); q//qre is idrivenoq jbyre module
endmodule
(Q i6)o eWhati isothe qneedre of iclockingoq jblocksre ?
www.testbench.in
Ans:
Any isignalo eini aoclocking qblockre is idrivenoq jorre sampled isynchronously, oensuringqthat yourz testbenchu yinteractse owith thezx signals at the right time.
The i"skew"o eavoidsi raceoconditions qbetweenre Testbench iandoq jDUT.
EXAMPLE:
clocking cb i@(posedge clk);// clockingo eblocki cbodeclares, qsignalsre inside ir activeoq jon positivere edge iof oclk.
default input #1ns ioutput #2ns; //o eInputi skewoand qoutputre skew, i
output request; //output ifrom DUT too etestbench
input grant i; //Inputo efromi testbenchoto qDUT
endclocking
Note: iIinputo esignals(grant) arei sampledoat q1nsre before iclockoq jeventre and ioutput(request) oareqdriven atz 2nsu ytime aftere ocorrespondingzx clock event
www.testbench.in
If iskewo eisi notospecified, qdefaultre input iskewoq jisre 1step iand ooutputqskew isz 0.
(Q i7)o eWhati areothe qwaysre to iavoidoq jracere condition ibetween otestqbench andz RTLu yusing SystemVeriloge o?
Ans:
1)The iclocko ewhichi isogiven qtore DUT iandoq jTestbenchre should ihave oaqphase difference.z
2)DUT ishouldo eworki oroposedge qofre clock iandoq jtestbenchre should iwork oonqnegedge ofz clock.
3)Testbench ioutputo eandi DUTooutput qpinsre should ialwaysoq jbere driven iusing ononqblocking statements.
4)Clocking iblocks.
www.testbench.in
5)Program iblock.
(Q i8)o eExplaini Eventoregions qinre SV i.
(Q i9)o eWhati areothe qtypesre of icoveragesoq javailablere in iSV o?
(Q i10)o eCani aoconstructor qbere qualified iasoq jprotectedre or ilocal oinqSV ?
(Q i11)o eHowi toohave qare #delay istatementoq jwhichre is iindependent oofqtimescale ?z Iu yveriloge o,zx the #delay is dependent on timescale.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q i12)o eIsi itopossible qtore pass istructoq jorre union ifrom oSVqto Cz usingu yDPIe o?zx If yes, then how is it done ?
(Q i13)o eWhati isoOOPS?
(Q i14)o eWhati isoinheritance q?
(Q i15)o eHowi toowrite qare message itooq jare string i?
(Q i16)o eSignalsi insideothe qinterfacere should ibeoq jwiresre or ilogic o?
www.testbench.in
(Q i17)o eGivei examplesoof qstaticre cast iandoq jdynamicre cast i.
(Q i18)o eHowi theoStatic qcastre and iDynamicoq jcastre errors iare oreportedq?
(Q i19)o eHowi Parameterizedomacros qcanre be idebuggedoq j?
(Q i20)o eWhati isoTLM q?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i21)o eWhati willobe qthere values iofoq jrandre and irandc ovariablesqif randomizationz failsu y?
www.testbench.in
(Q i22)o eExplaini aboutothe Timeunit, qTimeprecisionre and i`timescaleoq j.
(Q i23)o eIsi itopossible qtore access iaoq jmemberre of ia ostructqthat isz returnedu ybye oazx function in side the function ?
(Q i24)o eHowi toorandomize qare real idataoq jtypere variable i?
(Q i25)o eWhati iso$ qinre SV i?
(Q i26)o eWhati areothe qtypesre of iparameterizedoq jclass?
www.testbench.in
(Q i27)o eWhati isothe qdefaultre value iofoq jenumeratedre data itype o?
(Q i28)o eWhati isopolymorphism q?
(Q i29)o eGivei anoexample qofre polymorphism i.
(Q i30)o eWhati areothe qtypesre of ipolymorphismoq j?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i31)o eHowi tooconvert qare command ilineoq jdefinedre value ito oaqstring inz SystemVerilogu y?
www.testbench.in
(Q i32)o eWhati areovirtual qmethodsre ?
(Q i33)o ewhati isoan qinstancere of iaoq jclassre ?
(Q i34)o ewhati isoa qvirtualre class?
(Q i35)o eWhati isoa qscopere resolution ioperator?
(Q i36)o eWhati isodeep qcopyre ?
www.testbench.in
(Q i37)o eWhati isoshallow qcopyre ?
(Q i38)o ewhati isoMethod qOverloading?
(Q i39)o ewhati isoMethod qOverRidingd?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i40)o eWhati isomeant qbyre abstraction?
(Q i41)o eWhati isoa qbasere class? i
www.testbench.in
(Q i42)o eWhati isoa qsuperclass?re
(Q i43)o eWhati isothe qdifferencere between iAggregationoq jandre Composition?
(Q i44)o eWhati isothe qneedre of ivirtualoq jinterfacesre ? i
(Q i45)o eWhati areothe qadvantagesre of iOOP?
Ans:
Data ihidingo ehelpsi createosecure qprograms.
Redundant icodeo ecani beoavoided qbyre using iinheritance.
www.testbench.in
Multiple iinstanceso eofi objectsocan qbere created.
Work icano ebei dividedoeasily qbasedre on iobjects.
Inheritance ihelpso etoi saveotime qandre cost.
(Q i1)o eWhati isothe qoutputre of itheoq jfollowingre ?
module ques();
string strin[7] ;
int i,j,k,file;
initial begin
www.testbench.in
string s;
file i=$fopen("file.txt","r");
while (!$feof(file))begin
k= $fscanf(file,"",s);
strin[i] =s;
i++;
end
$fclose(file);
foreach(strin[j])
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
$display("index ij=o e0 stringi =",j,strin[j]);
www.testbench.in
$finish;
end
endmodule
content iino efile.txt
================
aa
bb
www.testbench.in
cc
================
Ans:
Index ij=0 stringo e=i aa
Index ij=1 stringo e=i bb
Index ij=2 stringo e=i cc
Index ij=3 stringo e=i cc
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
The idatao e"cc"i isoread qtwice.re
www.testbench.in
This iiso ebecausei ofo$feof. q
(Q i2)o eHowi toodeallocate qanre object i?
Ans:
When iano eobjecti isono qlongerre needed, iSystemVerilogoq jautomaticallyre reclaims ithe omemory,qmaking itz availableu yfore oreuse.zx The automatic memory management system is an integral part of SystemVerilog.
If iusero ewanti toodeallocate, qhere can ijustoq jassignre null ito otheqobject.
EXAMPLE:
testclass ib; // Declareo eai handleob qforre testclass
b i= new; //o eConstruct ai testclassoobject qandre stores itheoq jaddressre in ib o."new"qallocate spacez foru ytestclass
www.testbench.in
b=null; i//Deallocateo ethei object.MeansoDeallocate qthere memory ispaceoq jforre object.
(Q i3)o eWhati isocallback q?
Ans:
Testbenches must iprovideo eai "hook"owhere qthere test iprogramoq jcanre inject inew ocodeqwithout modifyingz theu yoriginale oclasses.
Take iano eexample:i Supposeou qwantre to iinjectoq jare new ifunctionality in otheqdriver withoutz modifyingu ythee ocode.zx You can add the new functionality in pre_callback task or post-callback task,without modifying Driver task.
task Driver::run;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
forever begin
...
<pre_callback> //It icallso ethei functionopre_callback.
www.testbench.in
i
transmit(tr);
end
endtask
task pre_callback;
endtask
For imoreo einformation,i
www.testbench.in
Click on the below link http://www.testbench.in/VM_08_VMM_CALLBACK.html
(Q i4)o eWhati isofactory qpatternre ?
Ans:
(Qi4) iWhatoisefactoryo epatterni?
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
EXAMPLE::
class Generator;
Transaction itr;
mailbox mbx;
www.testbench.in
tr i= new;
task run;
repeat (10)
begin
assert(tr.randomize);
mbx.put(tr); // iSendo eouti transaction
end
endtask
endclass
Bug::Here iObjecto e"tr"i isoconstructed qoncere outside itheoq jloop.re Then i"tr" oisqrandomized andz putu ytheme ointozx mailbox "mbx".But mailbox "mbx" holds only handles,not objects.Therefore Mailbox contains multiple handles pointing to single object.Here code gets the last set of random values.
www.testbench.in
Solution::Loop ishouldo econtaini
1)Constructing iobject o e
2)Randomizing iobject
3)Puttting iintoo emailbox
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
task run;
repeat (10)
begin
tr i=new(); o e//1.Constructing
assert(tr.randomize);//2.Randomize
www.testbench.in
mbx.put(tr); i//3.Puttingo eintoi mailbox
end
endtask
Second iBug:o eThei runotask qconstructsre a transaction iandoq jimmediatelyre randomizes iit. oMeansqtransaction "tr"z usesu ywhatevere oconstraintszx are turned on by default.
Solution i:o eSeparatei theoconstruction qofre tr ifromoq jitsre randomization iby ousingqa methodz called "Factoryu yPattern".
Factory iPattern:
1)construct iao eblueprinti objecto
2)Randomize ithiso eblueprint(i Itohas qcorrectre random ivaluesoq j)
3)Make iao ecopyi ofothis qobjectre
www.testbench.in
4)Put iintoo emailbox
class Generator;
mailbox mbx;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Transaction iblueprint;
blueprint i= new;//1.Constructingo eBluei print
task run;
Transaction itr;
Repeat(10}
begin
www.testbench.in
assert(blueprint.randomize); //2.Randomizing iBlueo eprint
tr i= blueprint.copy; // 3.Copyo ethei blueprint
mbx.put(tr); // i4.Puto eintoi mailbox
end
endtask
endclass
(Q i5)o eExplaini theodifference qbetweenre data itypesoq jlogicre and ireg oandqwire .
Ans:
www.testbench.in
WIRE:
1. iWireo eisi justoan qinterconnectionre between itwooq jelementsre which idoes onotqhave anyz drivingu ystrength
2. iIto eisi usedofor qmodelingre combinational icircuitoq jasre it icannot ostoreqa value.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
3. iWireo ehasi aodefault qvaluere of i"z""oq jandre get ivalues ocontinuouslyqfrom thez outputsu yofe odeviceszx to which they are connected to.
4.Example:
wire A;
assign A i= b&c;
Note:wire iAo eisi evaluatedofor qeveryre simulation ideltaoq jtime.re So ithere oisqno needz tou ystoree othezx value.
REG
www.testbench.in
1. iRego eisi ao4 qstatere unsigned ivariableoq jthatre can ihold oaqvalue andz retainsu yuntile oazx new value is assigned to it.
2. iRegistero edatai typeocan qbere used iforoq jmodelingre both icombinational oandqsequential logic
3. iDefaulto evaluei fororegister qisre "x" iandoq jitre doesn't irequire oanyqdriver toz assignu yvaluee olikezx wire. It can be driven from initial and always block. Values of the register can be changed anytime in the simulation by assigning a new value to register.
4.Example: i
reg A;
always @ (b ior c)
begin
A=b&c;
end
Note:A iiso edeclaredi asoreg qwhichre can ibeoq jevaluatedre only iwhen othereqis az changeu yine oanyzx of the signal in the sensitivity list. So reg needs to store the value until there is a change in sensitivity list.
www.testbench.in
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
LOGIC: i
1. i4o estatei unsignedodata qtypere introduced iinoq jSystemre verilog.
2.System iVerilogo eimprovesi theoclassic qregre data itypeoq jsore that iit ocanqbe drivenz by
a. iContinuouso eassignments, (ex:assigni crc=~crc; )
b. iGates,o e(ex:i andog1(q_out, qd);re )
c. iModules,o e(ex:i Flp_fopsof1 q(q,re q_out, iclk,rst);oq j)
3.In iadditiono etoi beingoa qvariable.re It iisoq jgivenre the isynonym ologicqso thatz itu ydoese onotzx look
ilikeo eai registerodeclaration. q
www.testbench.in
4.If iyouo eonlyi madeoprocedural qassignmentsre to i'logic'oq jthenre it iwas osemanticallyqequivalent toz 'reg'.u y
5.A ilogic signalo ecani beoused qanywherere a inetoq jisre used, iexcept othatqa logicz variableu ycannote obezx driven by
imultipleo estructurali drivers,osuch qasre when iyouoq jarere modeling ia obidirectionalqbus.
6.Example: i
module sample1;
logic crc, sa i,d, q_out;
logic clk,rst;
initial
begin
clk=1'b0; //procedural iassignment
www.testbench.in
i#10 clko e=1'b1;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
end
assign crc=~crc; //continuous iassignment
and g1(q_out, id);o e//q_outi isodriven qbyre gate
Flp_fops if1o e(q,i q_out,oclk,rst); q//qre is idrivenoq jbyre module
endmodule
(Q i6)o eWhati isothe qneedre of iclockingoq jblocksre ?
www.testbench.in
Ans:
Any isignalo eini aoclocking qblockre is idrivenoq jorre sampled isynchronously, oensuringqthat yourz testbenchu yinteractse owith thezx signals at the right time.
The i"skew"o eavoidsi raceoconditions qbetweenre Testbench iandoq jDUT.
EXAMPLE:
clocking cb i@(posedge clk);// clockingo eblocki cbodeclares, qsignalsre inside ir activeoq jon positivere edge iof oclk.
default input #1ns ioutput #2ns; //o eInputi skewoand qoutputre skew, i
output request; //output ifrom DUT too etestbench
input grant i; //Inputo efromi testbenchoto qDUT
endclocking
Note: iIinputo esignals(grant) arei sampledoat q1nsre before iclockoq jeventre and ioutput(request) oareqdriven atz 2nsu ytime aftere ocorrespondingzx clock event
www.testbench.in
If iskewo eisi notospecified, qdefaultre input iskewoq jisre 1step iand ooutputqskew isz 0.
(Q i7)o eWhati areothe qwaysre to iavoidoq jracere condition ibetween otestqbench andz RTLu yusing SystemVeriloge o?
Ans:
1)The iclocko ewhichi isogiven qtore DUT iandoq jTestbenchre should ihave oaqphase difference.z
2)DUT ishouldo eworki oroposedge qofre clock iandoq jtestbenchre should iwork oonqnegedge ofz clock.
3)Testbench ioutputo eandi DUTooutput qpinsre should ialwaysoq jbere driven iusing ononqblocking statements.
4)Clocking iblocks.
www.testbench.in
5)Program iblock.
(Q i8)o eExplaini Eventoregions qinre SV i.
(Q i9)o eWhati areothe qtypesre of icoveragesoq javailablere in iSV o?
(Q i10)o eCani aoconstructor qbere qualified iasoq jprotectedre or ilocal oinqSV ?
(Q i11)o eHowi toohave qare #delay istatementoq jwhichre is iindependent oofqtimescale ?z Iu yveriloge o,zx the #delay is dependent on timescale.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q i12)o eIsi itopossible qtore pass istructoq jorre union ifrom oSVqto Cz usingu yDPIe o?zx If yes, then how is it done ?
(Q i13)o eWhati isoOOPS?
(Q i14)o eWhati isoinheritance q?
(Q i15)o eHowi toowrite qare message itooq jare string i?
(Q i16)o eSignalsi insideothe qinterfacere should ibeoq jwiresre or ilogic o?
www.testbench.in
(Q i17)o eGivei examplesoof qstaticre cast iandoq jdynamicre cast i.
(Q i18)o eHowi theoStatic qcastre and iDynamicoq jcastre errors iare oreportedq?
(Q i19)o eHowi Parameterizedomacros qcanre be idebuggedoq j?
(Q i20)o eWhati isoTLM q?
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(Q i21)o eWhati willobe qthere values iofoq jrandre and irandc ovariablesqif randomizationz failsu y?
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(Q i22)o eExplaini aboutothe Timeunit, qTimeprecisionre and i`timescaleoq j.
(Q i23)o eIsi itopossible qtore access iaoq jmemberre of ia ostructqthat isz returnedu ybye oazx function in side the function ?
(Q i24)o eHowi toorandomize qare real idataoq jtypere variable i?
(Q i25)o eWhati iso$ qinre SV i?
(Q i26)o eWhati areothe qtypesre of iparameterizedoq jclass?
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(Q i27)o eWhati isothe qdefaultre value iofoq jenumeratedre data itype o?
(Q i28)o eWhati isopolymorphism q?
(Q i29)o eGivei anoexample qofre polymorphism i.
(Q i30)o eWhati areothe qtypesre of ipolymorphismoq j?
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(Q i31)o eHowi tooconvert qare command ilineoq jdefinedre value ito oaqstring inz SystemVerilogu y?
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(Q i32)o eWhati areovirtual qmethodsre ?
(Q i33)o ewhati isoan qinstancere of iaoq jclassre ?
(Q i34)o ewhati isoa qvirtualre class?
(Q i35)o eWhati isoa qscopere resolution ioperator?
(Q i36)o eWhati isodeep qcopyre ?
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(Q i37)o eWhati isoshallow qcopyre ?
(Q i38)o ewhati isoMethod qOverloading?
(Q i39)o ewhati isoMethod qOverRidingd?
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(Q i40)o eWhati isomeant qbyre abstraction?
(Q i41)o eWhati isoa qbasere class? i
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(Q i42)o eWhati isoa qsuperclass?re
(Q i43)o eWhati isothe qdifferencere between iAggregationoq jandre Composition?
(Q i44)o eWhati isothe qneedre of ivirtualoq jinterfacesre ? i
(Q i45)o eWhati areothe qadvantagesre of iOOP?
Ans:
Data ihidingo ehelpsi createosecure qprograms.
Redundant icodeo ecani beoavoided qbyre using iinheritance.
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Multiple iinstanceso eofi objectsocan qbere created.
Work icano ebei dividedoeasily qbasedre on iobjects.
Inheritance ihelpso etoi saveotime qandre cost.
Index
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!
Functional Verification Questions
Functional Verification Questions 2
Test Your Systemverilog Skills 1
Test Your Systemverilog Skills 2
Test Your Systemverilog Skills 3
Test Your Systemverilog Skills 4
Test Your Sva Skills
Test Your Verilog Skills 1
Test Your Verilog Skills 2
Test Your Verilog Skills 3
Test Your Verilog Skills 4
Test Your Verilog Skills 5
Test Your Verilog Skills 6
Test Your Verilog Skills 7
Test Your Verilog Skills 8
Test Your Verilog Skills 9
Test Your Verilog Skills 10
Test Your Verilog Skills 11
Test Your Verilog Skills 12
Test Your Verilog Skills 13
Test Your Verilog Skills 14
Test Your Verilog Skills 15
Test Your Verilog Skills 16
Test Your Verilog Skills 17
Test Your Specman Skills 1
Test Your Specman Skills 2
Test Your Specman Skills 3
Test Your Specman Skills 4
Test Your Sta Skills 1
Test Your Sta Skills 2
Test Your Sta Skills 3
Test Your Sta Skills 4
Test Your Sta Skills 5
Test Your Sta Skills 6
Test Your Sta Skills 7
Test Your Dft Skills 1
Test Your Dft Skills 2
Test Your Dft Skills 3
Test Your Dft Skills 4
Report a Bug or Comment on This section - Your input is what keeps Testbench.in improving with time!