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TITBITS
The first constraint program which wrote randomized sucessfully but the results are not what expected.
My constraint is to limit Var between 0 and 100.
EXAMPLE:
class Base;
rand integer Var;
constraint randge { 0< Var < 100 ;}
endclass
program inhe_109;
Base obj;
initial
begin
obj = new();
for(int i=0 ; i < 100 ; i++)
if(obj.randomize())
$display(" Randomization successful : Var = %0d ",obj.Var);
else
$display("Randomization failed");
end
endprogram
RESULTS:
Randomization successful : Var = 2026924861
Randomization successful : Var = -1198182564
Randomization successful : Var = 1119963834
Randomization successful : Var = -21424360
Randomization successful : Var = -358373705
Randomization successful : Var = -345517999
Randomization successful : Var = -1435493197
..etc
The mistake what I have done is simple,this resulted the constraint solver to solve the statement
(((0 < Var) < 100))
For the above equation, are the results are correct.
Then I changed the constraint to { 0< Var ;Var < 100 ;}
The solver considered the this constraint as (0 < Var) && (Var < 100); and solution are correct.
To generate random values less then -10,the following may not work.
EXAMPLE:
class Base_110;
rand integer Var;
constraint randge { Var + 10 <= 0 ;}
endclass
RESULTS:
Randomization sucsessfull : Var = -1601810394
Randomization sucsessfull : Var = 2147483646
Randomization sucsessfull : Var = -335544322
Var = 2147483646 is not less -10, but the solver solved it using ((Var + 10) <= 0) i.e ((2147483646 + 10) <= 0) which is true
To solve this use the inside operator.
constraint randge { Var inside {[-10000:-10]};}
Make sure that constraint expression are not mixed up with signed and unsigned variables.
# Ran_Stb_1.Var : 4
# Ran_Stb_1.Var : 5
# Ran_Stb_1.Var : 1
# Ran_Stb_1.Var : 1
# Ran_Stb_1.Var : 0
# Ran_Stb_1.Var : 2
# Ran_Stb_1.Var : 2
# Ran_Stb_1.Var : 7
# Ran_Stb_1.Var : 6
# Ran_Stb_1.Var : 0
Constraining Non Integral Data Types:
Constraints can be any SystemVerilog expression with variables and constants of integral type (e.g.,
bit, reg, logic, integer, enum, packed struct).
To Constraint a real number, randomize integer and convert it to real as it is required.
EXAMPLE:
class cls;
rand integer Var;
endclass
class real_c;
real r;
rand integer i;
rand integer j;
function void post_randomize;
r = $bitstoreal({i,j});
$display("%e ",r);
endfunction
endclass
program real_p_111;
real_c obj = new();
initial
repeat(5)
void'(obj.randomize());
endprogram
RESULT:
2.507685e-280
-1.188526e-07
9.658227e-297
-2.912335e+247
2.689449e+219
Saving Memory
In packet protocol application like PCI Express, the packets which are driven to the DUV has to be manipulated and stored to compare with the actual packet which is coming from DUV. If the packet size is large and number of packets are huge, it occupies more momery. In verilog in this case the whole packet need to be stored. HVL has more advantages w.r.t this case. We can store high level information like packet size, CRC error, header. But functional verification needs to store the payload for checking that the payload did not get corrupted. Major part of the storage taken by the payload itself. If we can avoid storing the payload, we can save lot of storage space.
The following technique assigns predictable random values to payload fields. Only the start of the payload need to be stored.
EXAMPLE:
integer pkt_length;
byte payload[0:MAX];
task gen_payload(integer seed ,integer length);
integer temp_seed;
temp_seed = seed;
for(int i=0;i< length;i++)
begin
temp_seed = $random(temp_seed);
payload[i] = temp_seed;
end
endtask
This is the task which checks whether payload is recived didnot get corrupted.
EXAMPLE:
task check_payload(integer seed,integer length);
integer temp_seed;
temp_seed = seed;
for(int i=0;i< length;i++)
begin
temp_seed = $random(temp_seed);
if(payload[i] != temp_seed)
$display(" ERROR :: DATA MISMATCH ");
end
endtask
The first constraint program which wrote randomized sucessfully but the results are not what expected.
My constraint is to limit Var between 0 and 100.
EXAMPLE:
class Base;
rand integer Var;
constraint randge { 0< Var < 100 ;}
endclass
program inhe_109;
Base obj;
initial
begin
obj = new();
for(int i=0 ; i < 100 ; i++)
if(obj.randomize())
$display(" Randomization successful : Var = %0d ",obj.Var);
else
$display("Randomization failed");
end
endprogram
RESULTS:
Randomization successful : Var = 2026924861
Randomization successful : Var = -1198182564
Randomization successful : Var = 1119963834
Randomization successful : Var = -21424360
Randomization successful : Var = -358373705
Randomization successful : Var = -345517999
Randomization successful : Var = -1435493197
..etc
The mistake what I have done is simple,this resulted the constraint solver to solve the statement
(((0 < Var) < 100))
For the above equation, are the results are correct.
Then I changed the constraint to { 0< Var ;Var < 100 ;}
The solver considered the this constraint as (0 < Var) && (Var < 100); and solution are correct.
To generate random values less then -10,the following may not work.
EXAMPLE:
class Base_110;
rand integer Var;
constraint randge { Var + 10 <= 0 ;}
endclass
RESULTS:
Randomization sucsessfull : Var = -1601810394
Randomization sucsessfull : Var = 2147483646
Randomization sucsessfull : Var = -335544322
Var = 2147483646 is not less -10, but the solver solved it using ((Var + 10) <= 0) i.e ((2147483646 + 10) <= 0) which is true
To solve this use the inside operator.
constraint randge { Var inside {[-10000:-10]};}
Make sure that constraint expression are not mixed up with signed and unsigned variables.
# Ran_Stb_1.Var : 4
# Ran_Stb_1.Var : 5
# Ran_Stb_1.Var : 1
# Ran_Stb_1.Var : 1
# Ran_Stb_1.Var : 0
# Ran_Stb_1.Var : 2
# Ran_Stb_1.Var : 2
# Ran_Stb_1.Var : 7
# Ran_Stb_1.Var : 6
# Ran_Stb_1.Var : 0
Constraining Non Integral Data Types:
Constraints can be any SystemVerilog expression with variables and constants of integral type (e.g.,
bit, reg, logic, integer, enum, packed struct).
To Constraint a real number, randomize integer and convert it to real as it is required.
EXAMPLE:
class cls;
rand integer Var;
endclass
class real_c;
real r;
rand integer i;
rand integer j;
function void post_randomize;
r = $bitstoreal({i,j});
$display("%e ",r);
endfunction
endclass
program real_p_111;
real_c obj = new();
initial
repeat(5)
void'(obj.randomize());
endprogram
RESULT:
2.507685e-280
-1.188526e-07
9.658227e-297
-2.912335e+247
2.689449e+219
Saving Memory
In packet protocol application like PCI Express, the packets which are driven to the DUV has to be manipulated and stored to compare with the actual packet which is coming from DUV. If the packet size is large and number of packets are huge, it occupies more momery. In verilog in this case the whole packet need to be stored. HVL has more advantages w.r.t this case. We can store high level information like packet size, CRC error, header. But functional verification needs to store the payload for checking that the payload did not get corrupted. Major part of the storage taken by the payload itself. If we can avoid storing the payload, we can save lot of storage space.
The following technique assigns predictable random values to payload fields. Only the start of the payload need to be stored.
EXAMPLE:
integer pkt_length;
byte payload[0:MAX];
task gen_payload(integer seed ,integer length);
integer temp_seed;
temp_seed = seed;
for(int i=0;i< length;i++)
begin
temp_seed = $random(temp_seed);
payload[i] = temp_seed;
end
endtask
This is the task which checks whether payload is recived didnot get corrupted.
EXAMPLE:
task check_payload(integer seed,integer length);
integer temp_seed;
temp_seed = seed;
for(int i=0;i< length;i++)
begin
temp_seed = $random(temp_seed);
if(payload[i] != temp_seed)
$display(" ERROR :: DATA MISMATCH ");
end
endtask