`timescale 1ns/1ns

module top();

reg Clk_125M;

wire        Reset          ;
reg        Clk_user        ;
reg        Clk_reg          ;

wire  [2:0]   Speed       ;
wire          Rx_mac_ra   ;
wire           Rx_mac_rd  ;
wire  [31:0]  Rx_mac_data ;
wire  [1:0]   Rx_mac_BE   ;
wire          Rx_mac_pa   ;
wire          Rx_mac_sop  ;
wire          Rx_mac_eop  ;
wire          Tx_mac_wa   ;
wire           Tx_mac_wr  ;
wire   [31:0]  Tx_mac_data;
wire   [1:0]   Tx_mac_BE  ;
wire           Tx_mac_sop ;
wire           Tx_mac_eop ;
wire          Gtx_clk     ;
wire           Rx_clk     ;
wire           Tx_clk     ;
wire          Tx_er       ;
wire          Tx_en       ;
wire  [7:0]   Txd         ;
wire           Rx_er      ;
wire           Rx_dv      ;
wire   [7:0]   Rxd        ;
wire           Crs        ;
wire           Col        ;
wire           CSB        ;
wire           WRB        ;
wire   [15:0]  CD_in      ;
wire  [15:0]  CD_out      ;
wire   [7:0]   CA         ;
wire           Mdio       ;
wire          Mdc         ;

initial
begin
Clk_125M = 0;
forever
#4 Clk_125M = ~ Clk_125M;
end

initial
$vcdpluson;


initial
  forever
  begin
  #4    Clk_user=0;
  #4    Clk_user=1;
  end

initial
forever
begin
#10    Clk_reg=0;
#10    Clk_reg=1;
end

main vshell (
.SystemClock(Clk_125M),
.\phy_intf.clk (Clk_125M),
.\phy_intf.Tx_er (Tx_er),
.\phy_intf.Tx_en (Tx_en),
.\phy_intf.Txd                      (Txd),
.\phy_intf.Rx_er                        (Rx_er),
.\phy_intf.Rx_dv                        (Rx_dv),
.\phy_intf.Rxd                      (Rxd),
.\phy_intf.Crs                      (Crs),
.\phy_intf.Col                      (Col),
.\phy_intf.Speed                        (Speed),
.\host_intf.Reset              (Reset),
.\host_intf.clk (Clk_125M),
.\host_intf.CPU_init_end                   (CPU_init_end               ),
.\host_intf.Rx_mac_ra                  (Rx_mac_ra              ),
.\host_intf.Rx_mac_rd                  (Rx_mac_rd              ),
.\host_intf.Rx_mac_data              (Rx_mac_data          ),
.\host_intf.Rx_mac_BE                  (Rx_mac_BE              ),
.\host_intf.Rx_mac_pa                  (Rx_mac_pa              ),
.\host_intf.Rx_mac_sop                  (Rx_mac_sop              ),
.\host_intf.Rx_mac_eop                  (Rx_mac_eop              ),
.\host_intf.Tx_mac_wa                      (Tx_mac_wa                  ),
.\host_intf.Tx_mac_wr                      (Tx_mac_wr                  ),
.\host_intf.Tx_mac_data                  (Tx_mac_data              ),
.\host_intf.Tx_mac_BE                  (Tx_mac_BE              ),
.\host_intf.Tx_mac_sop                      (Tx_mac_sop                  ),
.\host_intf.Tx_mac_eop                  (Tx_mac_eop              ),
.\cfg_intf.clk              (  Clk_reg        ),
.\cfg_intf.CD_out           (  CD_out       ),
.\cfg_intf.CSB              (  CSB          ),
.\cfg_intf.WRB              (  WRB          ),
.\cfg_intf.CPU_init_end     (  CPU_init_end ),
.\cfg_intf.CD_in            (  CD_in        ),
.\cfg_intf.CA               (  CA           )

);


always@(Rx_dv)
$display(" FROM TOP 0",Rx_dv);


MAC_top U_MAC_top(
.Reset                  (Reset              ),
.Clk_125M                (Clk_125M            ),
.Clk_user                (Clk_user            ),
.Clk_reg              (Clk_reg          ),
.Speed                          (Speed                      ),
.Rx_mac_ra                (Rx_mac_ra            ),
.Rx_mac_rd                (Rx_mac_rd            ),
.Rx_mac_data            (Rx_mac_data        ),
.Rx_mac_BE                (Rx_mac_BE            ),
.Rx_mac_pa                (Rx_mac_pa            ),
.Rx_mac_sop                (Rx_mac_sop            ),
.Rx_mac_eop                (Rx_mac_eop            ),
.Tx_mac_wa                    (Tx_mac_wa                ),
.Tx_mac_wr                    (Tx_mac_wr                ),
.Tx_mac_data                (Tx_mac_data            ),
.Tx_mac_BE                (Tx_mac_BE            ),
.Tx_mac_sop                    (Tx_mac_sop                ),
.Tx_mac_eop                (Tx_mac_eop            ),
.Gtx_clk              (Gtx_clk          ),
.Rx_clk                  (Clk_125M              ),
.Tx_clk                  (Tx_clk              ),
.Tx_er                  (Tx_er              ),
.Tx_en                  (Tx_en              ),
.Txd                (Txd            ),
.Rx_er                  (Rx_er              ),
.Rx_dv                  (Rx_dv              ),
.Rxd                (Rxd            ),
.Crs                (Crs            ),
.Col                (Col            ),
.CSB                            (CSB                        ),
.WRB                            (WRB                        ),
.CD_in                          (CD_in                      ),
.CD_out                         (CD_out                     ),
.CA                             (CA                         ),
.Mdio                          (Mdio                      ),
.Mdc                        (Mdc                    )
);




endmodule