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| `timescale 1ns/1ns module tb_top (); //****************************************************************************** //internal signals //****************************************************************************** //system signals reg Reset ; reg Clk_125M ; reg Clk_user ; reg Clk_reg ; wire [2:0] Speed ; wire Rx_mac_ra ; wire Rx_mac_rd ; wire [31:0] Rx_mac_data ; wire [1:0] Rx_mac_BE ; wire Rx_mac_pa ; wire Rx_mac_sop ; wire Rx_mac_eop ; wire Tx_mac_wa ; wire Tx_mac_wr ; wire [31:0] Tx_mac_data; wire [1:0] Tx_mac_BE ; wire Tx_mac_sop ; wire Tx_mac_eop ; wire Gtx_clk ; wire Rx_clk ; wire Tx_clk ; wire Tx_er ; wire Tx_en ; wire [7:0] Txd ; wire Rx_er ; wire Rx_dv ; wire [7:0] Rxd ; wire Crs ; wire Col ; wire CSB ; wire WRB ; wire [15:0] CD_in ; wire [15:0] CD_out ; wire [7:0] CA ; wire Mdio ; wire Mdc ; initial begin Reset =1; #20 Reset =0; end initial begin Clk_125M = 0; forever #4 Clk_125M = ~ Clk_125M; end //always // begin // #4 Clk_125M=0; // #4 Clk_125M=1; // end // ////always@(Clk_125M) ////$display("dfdf"); //always // begin // #5 Clk_user=0; // #5 Clk_user=1; // end // //always // begin // #10 Clk_reg=0; // #10 Clk_reg=1; // end /* MAC_top U_MAC_top( //system signals (//system signals ), .Reset (Reset ), .Clk_125M (Clk_125M ), .Clk_user (Clk_user ), .Clk_reg (Clk_reg ), .Speed (Speed ),Cr //user interface (//user interface ), .Rx_mac_ra (Rx_mac_ra ), .Rx_mac_rd (Rx_mac_rd ), .Rx_mac_data (Rx_mac_data ), .Rx_mac_BE (Rx_mac_BE ), .Rx_mac_pa (Rx_mac_pa ), .Rx_mac_sop (Rx_mac_sop ), .Rx_mac_eop (Rx_mac_eop ), //user interface (//user interface ), .Tx_mac_wa (Tx_mac_wa ), .Tx_mac_wr (Tx_mac_wr ), .Tx_mac_data (Tx_mac_data ), .Tx_mac_BE (Tx_mac_BE ), .Tx_mac_sop (Tx_mac_sop ), .Tx_mac_eop (Tx_mac_eop ), //Phy interface (//Phy interface ), //Phy interface (//Phy interface ), .Gtx_clk (Gtx_clk ), .Rx_clk (Rx_clk ), .Tx_clk (Tx_clk ), .Tx_er (Tx_er ), .Tx_en (Tx_en ), .Txd (Txd ), .Rx_er (Rx_er ), .Rx_dv (Rx_dv ), .Rxd (Rxd ), .Crs (Crs ), .Col (Col ), //host interface .CSB (CSB ), .WRB (WRB ), .CD_in (CD_in ), .CD_out (CD_out ), .CA (CA ), //MII interface signals (//MII interface signals ), .Mdio (Mdio ), .Mdc (Mdc ) ); */ main vshell ( .SystemClock(Clk_125M), //.phy_intf_clk(Clk_125M), //.phy_intf_Tx_er (Tx_er), //.phy_intf_Tx_en (Tx_en), //.phy_intf_Txd (Txd), //.phy_intf_Rx_er (Rx_er), //.phy_intf_Rx_dv (Rx_dv), //.phy_intf_Rxd (Rxd), //.phy_intf_Crs (Crs), //.phy_intf_Col (Col), //.phy_intf_Speed (Speed), //.host_intf_Reset (Reset), .host_intf_clk(Clk_125) //.host_intf_CPU_init_end (CPU_init_end ), //.host_intf_Rx_mac_ra (Rx_mac_ra ), //.host_intf_Rx_mac_rd (Rx_mac_rd ), //.host_intf_Rx_mac_data (Rx_mac_data ), //.host_intf_Rx_mac_BE (Rx_mac_BE ), //.host_intf_Rx_mac_pa (Rx_mac_pa ), //.host_intf_Rx_mac_sop (Rx_mac_sop ), //.host_intf_Rx_mac_eop (Rx_mac_eop ), //.host_intf_Tx_mac_wa (Tx_mac_wa ), //.host_intf_Tx_mac_wr (Tx_mac_wr ), //.host_intf_Tx_mac_data (Tx_mac_data ), //.host_intf_Tx_mac_BE (Tx_mac_BE ), //.host_intf_Tx_mac_sop (Tx_mac_sop ), //.host_intf_Tx_mac_eop (Tx_mac_eop ) // ); /* host_sim U_host_sim( .Reset (Reset ), .Clk_reg (Clk_reg ), .CSB (CSB ), .WRB (WRB ), .CD_in (CD_in ), .CD_out (CD_out ), .CPU_init_end (CPU_init_end ), .CA (CA ) ); */ endmodule |