Tutorials
MISC
Always Block In Classes
SystemVerilog doesnot allow to define always block in program block or class, as these are meant for testbench purpose.
Example to show the implimentation of always block in program block.
EXAMPLE:
program main;
integer a,b;
initial
repeat(4)
begin
#({$random()}%20)
a = $random();
#({$random()}%20)
b = $random();
end
initial
always_task();
task always_task();
fork
forever
begin
@(a,b);
$display(" a is %d : b is %d at %t ",a,b,$time);
end
join_none
endtask
endprogram
RESULT
a is -1064739199 : b is x at 8
a is -1064739199 : b is -1309649309 at 25
a is 1189058957 : b is -1309649309 at 42
a is 1189058957 : b is -1992863214 at 47
a is 114806029 : b is -1992863214 at 48
a is 114806029 : b is 512609597 at 66
a is 1177417612 : b is 512609597 at 75
a is 1177417612 : b is -482925370 at 84
Example to show the implimentation of always block in class.
EXAMPLE
class Base;
integer a,b;
task always_task();
fork
forever
begin
@(a,b);
$display(" a is %d : b is %d at %t ",a,b,$time);
end
join_none
endtask
endclass
program main;
initial
begin
Base obj;
obj = new();
// start the always block.
fork
obj.always_task();
join_none
repeat(4)
begin
#({$random()}%20)
obj.a = $random();
#({$random()}%20)
obj.b = $random();
end
end
endprogram
RESULT
a is -1064739199 : b is x at 8
a is -1064739199 : b is -1309649309 at 25
a is 1189058957 : b is -1309649309 at 42
a is 1189058957 : b is -1992863214 at 47
a is 114806029 : b is -1992863214 at 48
a is 114806029 : b is 512609597 at 66
a is 1177417612 : b is 512609597 at 75
a is 1177417612 : b is -482925370 at 84